Same opcodes, different instructions !

From: Ragnar (athragnar_at_yahoo.com)
Date: 11/28/03

  • Next message: pacman128_at_hotmail.com: "Re: Same opcodes, different instructions !" 
    Date: 28 Nov 2003 05:47:39 -0800

    Hello

    Consider these (with g++ 3.2, nasm 0.98.34, RH-9, IA-32)

    To access an auto var, g++ generates the instruction:

    mov eax, [ebp - 0x2c]

    which is asembled as 8B45D4. But when stepped through in bochs , this
    is disassembled (and executed) as

    mov eax, [ebp + 0xd4]

    Similarly,

    push dword [ebp - 0x2c]

    is assembled as FF75D4, which bochs shows as

    push [ebp + 0xd4]

    Also,

    lea eax, [ebp - 0x18]

    is assembled as 8D45E8 which bochs shows as

    lea eax, [ebp + 0xe8]

    This is giving page faults, and bochs seems to be correct as the
    behavior of the real hardware is isomorphic in this case to that of
    bochs; the same thing (page fault) happens on vmware, bochs and real
    hardware.

    This seems to be a bug, but i am not sure where (in my code or
    shudder, in g++ or Nasm). Just for checking, I wrote the instruction

    mov eax, [ebp + 0xd4]

    in Nasm, which assembled it as 8B85D4000000, and not as 8B85D4
    The default size bit in the code descriptor is set, so the offsets are
    32-bits.

    Can anyone suggest as to what the hell could be happening here.

    The same thing happens in g++ 2.96, RH 7. 

    --
Thanks & Regards
Ragnar
  • Next message: pacman128_at_hotmail.com: "Re: Same opcodes, different instructions !"

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