Re: intel 64 bit instructions vs amd 64 bit instructions

From: Andi Kleen (freitag_at_alancoxonachip.com)
Date: 09/19/04 

Date: Sun, 19 Sep 2004 13:38:01 +0200

"Chewy509" <Chewy509.doesnt.like.spam@austarnet.com.au> writes:
>
> As for AMD, I can't really say. But as a guess (since 40bit allows 1024GB
> physical), it's a compromise against maximising available physical RAM and
> keeping the number of pins to a minimum. (Since number of pins = more traces
> on the board = more cost for both AMD and the board manufacturer).

HyperTransport doesn't need more pins to transport wider addresses.

It's a packet switched protocol and the address is included in a
packet header. Data can be transported over multiple pins, but the
whole packet will be transmitted this way, not just the address. A CPU
link is normally 16bit wide, but some of the IO links are narrower
(8bits are common). But even the 8bit IO link has to transmit full
40bit addresses for DMA. You could even send a 40 bit address over a
1bit HyperTransport link (which has more than one pin though)

Newer revisions of the HyperTransport protocol have a special
"address extension" packet that allows to transport 64bit addresses.
However the current AMD CPUs don't support that.

Since the Opteron has a builtin memory controller there is a pin limit to the
maximum amount of RAM you can connect to a CPU. A single Opteron supports up
to 4 registered DDR DIMMs. The maximum memory supported in a system is
limited by the number of CPUs and the number of DIMMs

This currently limits an 4 CPU Opteron to 128GB = 37bits with 4GB DIMMs.

-Andi

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