Re: bits 32 oddities in NASM




Frank Kotler wrote:
James Daughtry wrote:

...
I was experimenting to see if I could use DOS interrupts with 32-bit
registers.

Yeah, you can. It was the "bits 32" that was killin' ya, not the 32-bit
registers. You can use 32-bit addressing modes in 16-bit code (but you
have to keep the total offset within the 64k-1 limit). This can be
*very* handy.

But, since dos (and bios) interrupts are 16-bit code, Nasm needs to be
generating 16-bit code to operate there. This means that using 32-bit
registers will require an "override prefix byte" - 66h for an operand
size, and 67h for address size. Nasm will generate these, where needed -
you don't have to do it. There's a slight "penalty" in terms of "bloat"
and speed, but the gains are often worthwhile.

Okay, but even though I'm using 32-bit addressing, the stack is still
scaled to 16-bits? The program works fine if I remove the bits
statement and change the 4's to 2's when scaling esp for the subroutine
argument. I'm curious why that is, and what else would be different.

.



Relevant Pages

  • Re: TI MSP430
    ... PDP-11 ISA, with slight changes (fewer addressing modes, allowing twice as many ... registers) to avoid patent issues... ... been a hack in the MOV instruction to allow @Rn and @Rn+ modes in the destination. ...
    (comp.arch.embedded)
  • Re: TI MSP430
    ... Of course, the architecture is a simplified version of the TMS9900 CPU, which was derived from the TI 990 minicomputer, which was in turn a rip-off of the PDP-11 ISA, with slight changes (fewer addressing modes, allowing twice as many registers) to avoid patent issues... ... modes of the msp430 really are appropriate for their target applications, or whether they would have been better off with the PDP-11 arrangement. ... as long as you have a stack pointer and push/pop instructions. ...
    (comp.arch.embedded)
  • Re: PIC vs ARM assembler (no flamewar please)
    ... addressing modes - you don't have to use half a dozen instructions just ... perhaps including the CPU32 addressing modes (all ... And having some more registers ... The ARM instruction set is not particularly nice for assembler ...
    (comp.arch.embedded)
  • Re: TI MSP430
    ... Of course, the architecture is a simplified version of the TMS9900 CPU, which was derived from the TI 990 minicomputer, which was in turn a rip-off of the PDP-11 ISA, with slight changes (fewer addressing modes, allowing twice as many registers) to avoid patent issues... ... modes of the msp430 really are appropriate for their target applications, or whether they would have been better off with the PDP-11 arrangement. ... well as a hypothetical MSP-430 which was closer in instruction design ...
    (comp.arch.embedded)
  • Re: TI MSP430
    ... Of course, the architecture is a simplified version of the TMS9900 CPU, which was derived from the TI 990 minicomputer, which was in turn a rip-off of the PDP-11 ISA, with slight changes (fewer addressing modes, allowing twice as many registers) to avoid patent issues... ... What is much more relevant is whether the register set and addressing modes of the msp430 really are appropriate for their target applications, or whether they would have been better off with the PDP-11 arrangement. ... The indirect modes are almost entirely superfluous when you have enough registers to hold pointers in registers, rather than having to have them in memory or on the stack. ...
    (comp.arch.embedded)