Re: Is it catachrestial as 'Effective Addresses' in NASM documentation?



Frank Kotler wrote:
Julienne Walker wrote:

...
one can easily see why lea exists:

mov ebx,mem
mov esi,2

; Simulate "lea edx[ebx+esi*4]"
mov edx,ebx
imul esi,4
add edx,esi

Stop right there! That's "lea".

mov eax,[edx] ; eax = 3

This is *not* part of what "lea" does. The confusing thing about "lea"
is that it *looks* like a memory instruction, but it's an arithmetic
instruction - just does the calculation, doesn't touch memory at all.

Sorry, the memory access wasn't meant to be a part of the lea
simulation at all. It just happened to be the next instruction since
all of the examples ended up accessing the effective address.
Consistency and whatnot. Would this work better?

; Simulate "lea edx[ebx+esi*4]"
mov edx,ebx
imul esi,4
add edx,esi

; Access the result
mov eax,[edx] ; eax = 3

.



Relevant Pages

  • Re: [Lit.] Buffer overruns
    ... > floating point support or a memory expansion option. ... had virtual memory support grafted on. ... > where the modified instruction was fetched from. ... vis-a-vis the official coporate strategic operating system TSS/360. ...
    (sci.crypt)
  • Re: [PATCH] Mantaining turnstile aligned to 128 bytes in i386 CPUs
    ... :This doesn't contradict your claim since main memory is not really involved. ... that gives the same not-very-real-world cache state for all iterations ... full, and the cpu stalls anyway. ... static instruction order makes it easiest for them, ...
    (freebsd-arch)
  • Re: [PATCH] Mantaining turnstile aligned to 128 bytes in i386 CPUs
    ... :This doesn't contradict your claim since main memory is not really involved. ... that gives the same not-very-real-world cache state for all iterations ... full, and the cpu stalls anyway. ... static instruction order makes it easiest for them, ...
    (freebsd-current)
  • Re: New ARM Cortex Microcontroller Product Family from STMicroelectronics
    ... FIFOs or instruction prefetching are not ... It is much better to just have single cycle ... memory. ... The Stellaris CM3 running at 50 ...
    (comp.arch.embedded)
  • Fourth edition of Computer Architecture: A Quantitative Approach
    ... Computer Architecture: ... Increased coverage on achieving parallelism with multiprocessors. ... Advanced Techniques for Instruction Delivery and Speculation ... Distributed Shared Memory and Directory-Based Coherence ...
    (comp.arch)