Re: I'm having trouble finding opcodes

corey wrote:

Where is hex BC? Anyone know?

Help please i'm trying to write a disassembler - I've managed it for
Z80 but I can't even start with x86.

It's all in the processor manual. Here a list which (at least I
think) is much better readable:


r0 (eax,ax,al)
r1 (edx,dx,dl)
r2 (ecx,cx,cl)
r3 (ebx,bx,bl)
r4 (ebp,bp) ; nur .w und .l
r5 (esi,si) ; nur .w und .l
r6 (edi,di) ; nur .w und .l
r7 (esp,sp) ; nur .w und .l
m0 (ah) ; nur .b
m1 (dh) ; nur .b
m2 (ch) ; nur .b
m3 (bh) ; nur .b




BEFEHLSFORMAT:
=============
Anzahl Bytes gueltige Werte
--------------------|----------------|--------------
Instruction Prefix | 0 oder 1 | $f3 (rep,repeq); $f2 (rep,repne);
| | $f0 (lock)
Addresssize Prefix | 0 oder 1 | $67
Operandsize Prefix | 0 oder 1 | $66
Segment Override | 0 oder 1 | $3e (s0); $26 (s1); $64 (s2);
| | $65 (s3); $2e (s6); $36 (s7);
Opcode | 1 oder 2 | siehe Tabelle Opcodes
ModR/M | 0 oder 1 | siehe Tabelle ModR/M
SIB | 0 oder 1 | siehe Tabelle SIB
Dispacement | 0,1,2 oder 4 | beliebig
Immediate | 0,1,2 oder 4 | beliebig



OPCODES:
=======

00 /r add.b rk,ADRS

01 /r add.w rk,ADRS
add.l rk,ADRS

02 /r add.b ADRS,rk

03 /r add.w ADRS,rk
add.l ADRS,rk

04 (ib) add.b #imm8, r0

05 (iw) add.w #imm16,r0
add.l #imm32,r0

06 move.w s1,-(sp)
move.l s1,-(sp)

07 move.w (sp)+,s1
move.l (sp)+,s1

08 /r or.b rk,ADRS

09 /r or.w rk,ADRS
or.l rk,ADRS

0a /r or.b ADRS,rk

0b /r or.w ADRS,rk
or.l ADRS,rk

0c (ib) or.b #imm8, r0

0d (iw) or.w #imm16,r0
or.l #imm32,r0

0e move.w s6,-(sp)

0f 00 /0 move.w ldtr,ADRS
/1 move.w tr,ADRS
/2 move.w ADRS,ldtr
/3 move.w ADRS,tr
/4 verr.w ADRS
/5 verw.w ADRS

0f 01 /0 move.w gdtr,MADRS
move.l gdtr,MADRS
/1 move.w idtr,MADRS
move.l idtr,MADRS
/2 move.w MADRS,gdtr
move.l MADRS,gdtr
/3 move.w MADRS,idtr
move.l MADRS,idtr
/4 move.w cr0,ADRS
/6 move.w ADRS,cr0

0f 02 /r lar.w ADRS,rk
lar.l ADRS,rk

0f 03 /r ldsl.w ADRS,rk
ldsl.l ADRS,rk

0f 06 bclr.w #3,cr0

0f 08 invl_cache

0f 09 invl_cache_wb

0f 20 /j move.l crj,rk (rk=ADRS: MOD=11 R/M=k)
0f 21 /j move.l drj,rk (rk=ADRS: MOD=11 R/M=k)
0f 22 /j move.l rk,crj (rk=ADRS: MOD=11 R/M=k)
0f 23 /j move.l rk,drj (rk=ADRS: MOD=11 R/M=k)
0f 24 /j move.l trj,rk (rk=ADRS: MOD=11 R/M=k)
0f 26 /j move.l rk,trj (rk=ADRS: MOD=11 R/M=k)

0f 80 cw bvs.w label
cl bvs.l label
0f 81 cw bvc.w label
cl bvc.l label
0f 82 cw bcs.w label
cl bcs.l label
0f 83 cw bcc.w label
cl bcc.l label
0f 84 cw beq.w label
cl beq.l label
0f 85 cw bne.w label
cl bne.l label
0f 86 cw bls.w label
cl bls.l label
0f 87 cw bhi.w label
cl bhi.l label
0f 88 cw bmi.w label
cl bmi.l label
0f 89 cw bpl.w label
cl bpl.l label
0f 8a cw bps.w label
cl bps.l label
0f 8b cw bpc.w label
cl bpc.l label
0f 8c cw blt.w label
cl blt.l label
0f 8d cw bge.w label
cl bge.l label
0f 8e cw ble.w label
cl ble.l label
0f 8f cw bgt.w label
cl bgt.l label

0f 90 svs.b ADRS
0f 91 svc.b ADRS
0f 92 scs.b ADRS
0f 93 scc.b ADRS
0f 94 seq.b ADRS
0f 95 sne.b ADRS
0f 96 sls.b ADRS
0f 97 shi.b ADRS
0f 98 smi.b ADRS
0f 99 spl.b ADRS
0f 9a sps.b ADRS
0f 9b spc.b ADRS
0f 9c slt.b ADRS
0f 9d sge.b ADRS
0f 9e sle.b ADRS
0f 9f sgt.b ADRS

0f a0 move.w s2,-(sp)
move.l s2,-(sp)
0f a1 move.w (sp)+,s2
move.l (sp)+,s2

0f a3 /r btst.w rk,ADRS
btst.l rk,ADRS

0f a4 /r ib dsl.w #imm8,ADRS<rk
dsl.l #imm8,ADRS<rk

0f a5 /r dsl.w r2,ADRS<rk
dsl.l r2,ADRS<rk

0f a8 move.w s3,-(sp)
move.l s3,-(sp)

0f a9 move.w (sp)+,s3
move.l (sp)+,s3

0f ab /r bset.w rk,ADRS
bset.l rk,ADRS

0f ac /r ib dsr.w #imm8,rk>ADRS
dsr.l #imm8,rk>ADRS

0f ad /r dsr.w r2,rk>ADRS
dsr.l r2,rk>ADRS

0f af /r muls.w ADRS,rk,rk
muls.l ADRS,rk,rk

0f b0 /r cas.b r0,rk,ADRS

0f b1 /r cas.w r0,rk,ADRS
cas.l r0,rk,ADRS

0f b2 /r move.w MADRS,s7|rk
move.l MADRS,s7|rk

0f b3 /r bclr.w rk,ADRS
bclr.l rk,ADRS

0f b4 /r move.w MADRS,s2|rk
move.l MADRS,s2|rk

0f b5 /r move.w MADRS,s3|rk
move.l MADRS,s3|rk

0f b6 /r movu.bw ADRS,rk
movu.bl ADRS,rk

0f b7 /r movu.wl ADRS,rk
(movu.ww ADRS,rk) ; = move.w ADRS,rk

0f ba /4 (ib) btst.w #imm8,ADRS
btst.l #imm8,ADRS

0f ba /5 (ib) bset.w #imm8,ADRS
bset.l #imm8,ADRS

0f ba /6 (ib) bclr.w #imm8,ADRS
bclr.l #imm8,ADRS

0f ba /7 (ib) bchg.w #imm8,ADRS
bchg.l #imm8,ADRS

0f bb /r bchg.w rk,ADRS
bchg.l rk,ADRS

0f bc /r bscf.w ADRS,rk
bscf.l ADRS,rk

0f bd /r bscr.w ADRS,rk
bscr.l ADRS,rk

0f be /r movs.bw ADRS,rk
movs.bl ADRS,rk

0f bf /r movs.wl ADRS,rk
(movs.ww ADRS,rk) ; = move.w ADRS,rk

0f c0 /r xadd.b rk,ADRS

0f c1 /r xadd.w rk,ADRS
xadd.l rk,ADRS

0f c8 bswap.l r0
0f c9 bswap.l r2
0f ca bswap.l r1
0f cb bswap.l r3
0f cc bswap.l r7
0f cd bswap.l r4
0f ce bswap.l r5
0f cf bswap.l r6

10 /r addc.b ri,ADRS

11 /r addc.w ri,ADRS
addc.l ri,ADRS

12 /r addc.b ADRS,ri

13 /r addc.w ADRS,ri
addc.l ADRS,ri

14 (ib) addc.b #imm8, r0

15 (iw) addc.w #imm16,r0
(il) addc.l #imm32,r0

16 move.w s7,-(sp)
move.l s7,-(sp)

17 move.w (sp)+,s7
move.l (sp)+,s7

18 /r subc.b ri,ADRS

19 /r subc.w ri,ADRS
subc.l ri,ADRS

1a /r subc.b ADRS,ri

1b /r subc.w ADRS,ri
subc.l ADRS,ri

1c (ib) subc.b #imm8, r0

1d (iw) subc.w #imm16,r0
(il) subc.l #imm32,r0

1e move.w s0,-(sp)
move.l s0,-(sp)

1f move.w (sp)+,s0
move.l (sp)+,s0

20 /r and.b ri,ADRS

21 /r and.w ri,ADRS
and.l ri,ADRS

22 /r and.b ADRS,ri

23 /r and.w ADRS,ri
and.l ADRS,ri

24 (ib) and.b #imm8, r0

25 (iw) and.w #imm16,r0
(il) and.l #imm32,r0

26 {s1}

27 adj_dec_add r0

28 /r sub.b ri,ADRS

29 /r sub.w ri,ADRS
sub.l ri,ADRS

2a /r sub.b ADRS,ri

2b /r sub.w ADRS,ri
sub.l ADRS,ri

2c (ib) sub.b #imm8, r0
2d (iw) sub.w #imm16,r0
(il) sub.l #imm32,r0

2e {s6}

2f adj_dec_sub r0

30 /r eor.b ri,ADRS

31 /r eor.w ri,ADRS
eor.l ri,ADRS
32 /r eor.b ADRS,ri

33 /r eor.w ADRS,ri
eor.l ADRS,ri
34 (ib) eor.b #imm8, r0

35 (iw) eor.w #imm16,r0
(il) eor.l #imm32,r0

36 {s7}

37 adj_asc_add r0

38 /r cmp.b ri,ADRS

39 /r cmp.w ri,ADRS
cmp.l ri,ADRS
3a /r cmp.b ADRS,ri

3b /r cmp.w ADRS,ri
cmp.l ADRS,ri
3c (ib) cmp.b #imm8, r0

3d (iw) cmp.w #imm16,r0
(il) cmp.l #imm32,r0

3e {s0}

3f adj_asc_sub r0

40 inc.w r0
inc.l r0
41 inc.w r2
inc.l r2
42 inc.w r1
inc.l r1
43 inc.w r3
inc.l r3
44 inc.w r7
inc.l r7
45 inc.w r4
inc.l r4
46 inc.w r5
inc.l r5
47 inc.w r6
inc.l r6

48 dec.w r0
dec.l r0
49 dec.w r2
dec.l r2
4a dec.w r1
dec.l r1
4b dec.w r3
dec.l r3
4c dec.w r7
dec.l r7
4d dec.w r4
dec.l r4
4e dec.w r5
dec.l r5
4f dec.w r6
dec.l r6

50 move.w r0,-(sp)
move.l r0,-(sp)

51 move.w r2,-(sp)
move.l r2,-(sp)

52 move.w r1,-(sp)
move.l r1,-(sp)

53 move.w r3,-(sp)
move.l r3,-(sp)

54 move.w r7,-(sp)
move.l r7,-(sp)

55 move.w r4,-(sp)
move.l r4,-(sp)

56 move.w r5,-(sp)
move.l r5,-(sp)

57 move.w r6,-(sp)
move.l r6,-(sp)

58 move.w (sp)+,r0
move.l (sp)+,r0

59 move.w (sp)+,r2
move.l (sp)+,r2

5a move.w (sp)+,r1
move.l (sp)+,r1

5b move.w (sp)+,r3
move.l (sp)+,r3

5c move.w (sp)+,r7
move.l (sp)+,r7

5d move.w (sp)+,r4
move.l (sp)+,r4

5e move.w (sp)+,r5
move.l (sp)+,r5

5f move.w (sp)+,r6
move.l (sp)+,r6

60 movem.w r0-r7,-(sp)
movem.l r0-r7,-(sp)

61 movem.w (sp)+,r0-r7
movem.l (sp)+,r0-r7

62 /r chk.w MADRS,rk
chk.l MADRS,rk

63 /r arpl.w rk,ADRS

64 {s2}

65 {s3}

66 operand-size prefix

67 address-size prefix

68 (iw) move.w #imm16,-(sp)
(il) move.l #imm32,-(sp)

69 /r (iw) muls.w #imm16,ADRS,rk
(il) muls.l #imm32,ADRS,rk

6a ib moveq.w #imm8,-(sp)
moveq.l #imm8,-(sp)

6b /r (ib) mulsq.w #imm8,ADRS,rk
mulsq.l #imm8,ADRS,rk

6c in.b r1,(r6.w)+-{s1}
in.b r1,(r6.l)+-{s1}

6d in.w r1,(r6.w)+-{s1}
in.w r1,(r6.l)+-{s1}
in.l r1,(r6.w)+-{s1}
in.l r1,(r6.l)+-{s1}

6e out.b (r5.w)+-{si},r1
out.b (r5.l)+-{si},r1

6f out.w (r5.w)+-{si},r1
out.w (r5.l)+-{si},r1
out.l (r5.w)+-{si},r1
out.l (r5.l)+-{si},r1

70 (cb) bvs.b label
71 (cb) bvc.b label
72 (cb) bcs.b label
73 (cb) bcc.b label
74 (cb) beq.b label
75 (cb) bne.b label
76 (cb) bls.b label
77 (cb) bhi.b label
78 (cb) bmi.b label
79 (cb) bpl.b label
7a (cb) bps.b label
7b (cb) bpc.b label
7c (cb) blt.b label
7d (cb) bge.b label
7e (cb) ble.b label
7f (cb) bgt.b label

80 /0 (ib) add.b #imm8,ADRS
/1 (ib) or.b #imm8,ADRS
/2 (ib) addc.b #imm8,ADRS
/3 (ib) subc.b #imm8,ADRS
/4 (ib) and.b #imm8,ADRS
/5 (ib) sub.b #imm8,ADRS
/6 (ib) eor.b #imm8,ADRS
/7 (ib) cmp.b #imm8,ADRS

81 /0 (iw) add.w #imm16,ADRS
(il) add.l #imm32,ADRS
/1 (iw) or.w #imm16,ADRS
(il) or.l #imm32,ADRS
/2 (iw) addc.w #imm16,ADRS
(il) addc.l #imm32,ADRS
/3 (iw) subc.w #imm16,ADRS
(il) subc.l #imm32,ADRS
/4 (iw) and.w #imm16,ADRS
(il) and.l #imm32,ADRS
/5 (iw) sub.w #imm16,ADRS
(il) sub.l #imm32,ADRS
/6 (iw) eor.w #imm16,ADRS
(il) eor.l #imm32,ADRS
/7 (iw) cmp.w #imm16,ADRS
(il) cmp.l #imm32,ADRS

82 (wie 80 ?)

83 /0 (ib) addq.w #imm8,ADRS
addq.l #imm8,ADRS
/1 (ib) orq.w #imm8,ADRS
orq.l #imm8,ADRS
/2 (ib) addcq.w #imm8,ADRS
addcq.l #imm8,ADRS
/3 (ib) subcq.w #imm8,ADRS
subcq.l #imm8,ADRS
/4 (ib) andq.w #imm8,ADRS
andq.l #imm8,ADRS
/5 (ib) subq.w #imm8,ADRS
subq.l #imm8,ADRS
/6 (ib) eorq.w #imm8,ADRS
eorq.l #imm8,ADRS
/7 (ib) cmpq.w #imm8,ADRS
cmpq.l #imm8,ADRS

84 /r tst.b rk,ADRS

85 /r tst.w rk,ADRS
tst.l rk,ADRS

86 /r exg.b rk,ADRS

87 /r exg.w rk,ADRS
exg.l rk,ADRS

88 /r move.b rk,ADRS

89 /r move.w rk,ADRS
move.l rk,ADRS

8a /r move.b ADRS,rk

8b /r move.w ADRS,rk
move.l ADRS,rk

8c /0 move.w s1,ADRS
/1 move.w s6,ADRS
/2 move.w s7,ADRS
/3 move.w s0,ADRS
/4 move.w s2,ADRS
/5 move.w s3,ADRS

8d /r lea.w MADRS,rk
lea.l MADRS,rk

8e /0 move.w ADRS,s1
/2 move.w ADRS,s7
/3 move.w ADRS,s0
/4 move.w ADRS,s2
/5 move.w ADRS,s3

8f /0 move.w (sp)+,ADRS
move.l (sp)+,ADRS

90 nop

91 exg.w r0,r2
exg.l r0,r2

92 exg.w r0,r1
exg.l r0,r1

93 exg.w r0,r3
exg.l r0,r3

94 exg.w r0,r7
exg.l r0,r7

95 exg.w r0,r4
exg.l r0,r4

96 exg.w r0,r5
exg.l r0,r5

97 exg.w r0,r6
exg.l r0,r6

98 ext.w r0
ext.l r0

99 ext.w r0,r0|r1
ext.l r0,r0|r1

9a (cd) jsr.ww segment:label
(cp) jsr.wl segment:label

9b wait

9c move.w sr,-(sp)
move.l sr,-(sp)

9d move.w (sp)+,sr
move.l (sp)+,sr

9e move.b m0,sr

9f move.b sr,m0

a0 (w) move.b OFF16{si},r0
(l) move.b OFF32{si},r0

a1 (w) move.w OFF16{si},r0
move.l OFF16{si},r0
(l) move.w OFF32{si},r0
move.l OFF32{si},r0

a2 (w) move.b r0,OFF16{si}
(l) move.b r0,OFF32{si}

a3 (w) move.w r0,OFF16{si}
move.l r0,OFF16{si}
(l) move.w r0,OFF32{si}
move.l r0,OFF32{si}

a4 move.b (r5.w)+-{si},(r6.w)+-{s1}
move.b (r5.l)+-{si},(r6.l)+-{s1}

a5 move.w (r5.w)+-{si},(r6.w)+-{s1}
move.w (r5.l)+-{si},(r6.l)+-{s1}
move.l (r5.w)+-{si},(r6.w)+-{s1}
move.l (r5.l)+-{si},(r6.l)+-{s1}

a6 cmp.b (r6.w)+-{s1},(r5.w)+-{si}
cmp.b (r6.l)+-{s1},(r5.l)+-{si}

a7 cmp.w (r6.w)+-{s1},(r5.w)+-{si}
cmp.w (r6.l)+-{s1},(r5.l)+-{si}
cmp.l (r6.w)+-{s1},(r5.w)+-{si}
cmp.l (r6.l)+-{s1},(r5.l)+-{si}

a8 (ib) tst.b #imm8,r0

a9 (iw) tst.w #imm16,r0
(il) tst.l #imm32,r0

aa move.b r0,(r6.w)+-{s1}
move.b r0,(r6.l)+-{s1}

ab move.w r0,(r6.w)+-{s1}
move.w r0,(r6.l)+-{s1}
move.l r0,(r6.w)+-{s1}
move.l r0,(r6.l)+-{s1}

ac move.b (r5.w)+-{si},r0
move.b (r5.l)+-{si},r0

ad move.w (r5.w)+-{si},r0
move.w (r5.l)+-{si},r0
move.l (r5.w)+-{si},r0
move.l (r5.l)+-{si},r0

ae cmp.b (r6.w)+-{s1},r0
cmp.b (r6.l)+-{s1},r0

af cmp.w (r6.w)+-{s1},r0
cmp.w (r6.l)+-{s1},r0
cmp.l (r6.w)+-{s1},r0
cmp.l (r6.l)+-{s1},r0

b0 (ib) move.b #imm8,r0
b1 (ib) move.b #imm8,r2
b2 (ib) move.b #imm8,r1
b3 (ib) move.b #imm8,r3
b4 (ib) move.b #imm8,m0
b5 (ib) move.b #imm8,m2
b6 (ib) move.b #imm8,m1
b7 (ib) move.b #imm8,m3

b8 (iw) move.w #imm16,r0
(il) move.l #imm32,r0
b9 (iw) move.w #imm16,r2
(il) move.l #imm32,r2
ba (iw) move.w #imm16,r1
(il) move.l #imm32,r1
bb (iw) move.w #imm16,r3
(il) move.l #imm32,r3
bc (iw) move.w #imm16,r7
(il) move.l #imm32,r7
bd (iw) move.w #imm16,r4
(il) move.l #imm32,r4
be (iw) move.w #imm16,r5
(il) move.l #imm32,r5
bf (iw) move.w #imm16,r6
(il) move.l #imm32,r6

c0 /0 (ib) rol.b #imm8,ADRS
/1 (ib) ror.b #imm8,ADRS
/2 (ib) rocl.b #imm8,ADRS
/3 (ib) rocr.b #imm8,ADRS
/4 (ib) lsl.b #imm8,ADRS
/5 (ib) lsr.b #imm8,ADRS
/6 (ib) asl.b #imm8,ADRS
/7 (ib) asr.b #imm8,ADRS

c1 /0 (ib) rol.w #imm8,ADRS
rol.l #imm8,ADRS
/1 (ib) ror.w #imm8,ADRS
ror.l #imm8,ADRS
/2 (ib) rocl.w #imm8,ADRS
rocl.l #imm8,ADRS
/3 (ib) rocr.w #imm8,ADRS
rocr.l #imm8,ADRS
/4 (ib) lsl.w #imm8,ADRS
lsl.l #imm8,ADRS
/5 (ib) lsr.w #imm8,ADRS
lsr.l #imm8,ADRS
/6 (ib) asl.w #imm8,ADRS
asl.l #imm8,ADRS
/7 (ib) asr.w #imm8,ADRS
asr.l #imm8,ADRS

c2 (iw) rts.w #imm16
rts.l #imm16

c3 rts.w
rts.l

c4 /r move.w MADRS,s1|rk
move.l MADRS,s1|rk
c5 /r move.w MADRS,s0|rk
move.l MADRS,s0|rk

c6 /x (ib) move.b #imm8,ADRS

c7 /x (iw) move.w #imm16,ADRS
(il) move.l #imm32,ADRS

c8 (iw) (ib) link.w r4,#imm16,#imm8
link.l r4,#imm16,#imm8

c9 unlk.w r4
unlk.l r4

ca (iw) rts.ww #imm16
rts.ll #imm16

cb rts.ww
rts.ll

cc trap #3

cd (ib) trap #imm8

ce trapv

cf rte.w
rte.l

d0 /0 rol.b #1,ADRS
/1 ror.b #1,ADRS
/2 rocl.b #1,ADRS
/3 rocr.b #1,ADRS
/4 lsl.b #1,ADRS
/5 lsr.b #1,ADRS
/6 asl.b #1,ADRS
/7 asr.b #1,ADRS

d1 /0 rol.w #1,ADRS
rol.l #1,ADRS
/1 ror.w #1,ADRS
ror.l #1,ADRS
/2 rocl.w #1,ADRS
rocl.l #1,ADRS
/3 rocr.w #1,ADRS
rocr.l #1,ADRS
/4 lsl.w #1,ADRS
lsl.l #1,ADRS
/5 lsr.w #1,ADRS
lsr.l #1,ADRS
/6 asl.w #1,ADRS
asl.l #1,ADRS
/7 asr.w #1,ADRS
asr.l #1,ADRS


d2 /0 rol.b r2,ADRS
/1 ror.b r2,ADRS
/2 rocl.b r2,ADRS
/3 rocr.b r2,ADRS
/4 lsl.b r2,ADRS
/5 lsr.b r2,ADRS
/6 asl.b r2,ADRS
/7 asr.b r2,ADRS

d3 /0 rol.w r2,ADRS
rol.l r2,ADRS
/1 ror.w r2,ADRS
ror.l r2,ADRS
/2 rocl.w r2,ADRS
rocl.l r2,ADRS
/3 rocr.w r2,ADRS
rocr.l r2,ADRS
/4 lsl.w r2,ADRS
lsl.l r2,ADRS
/5 lsr.w r2,ADRS
lsr.l r2,ADRS
/6 asl.w r2,ADRS
asl.l r2,ADRS
/7 asr.w r2,ADRS
asr.l r2,ADRS

d4 0a adj_asc_mul r0
(ib) adj_asc_mul #imm8,r0 (imm8 <> $0a)

d5 0a adj_asc_div r0
(ib) adj_asc_div #imm8,r0 (imm8 <> $0a)

d6 ext.b CARRY,r0 ; undokumentierter Befehl
; r0.b = 0 falls C=0
; r0.b = $ff falls C=1

d7 move.b (r3.w,r0.b){si},r0
move.b (r3.l,r0.b){si},r0

d8 \
d9 \
da |
db \ Escape to
dc / Coprozessor
dd |
de /
df /

e0 (cb) dbeq.w r2,label
dbeq.l r2,label

e1 (cb) dbne.w r2,label
dbne.l r2,label

e2 (cb) dbf.w r2,label
dbf.l r2,label

e3 (cb) beqr2w.b label
beqr2l.b label

e4 (ib) in.b #imm8,r0

e5 (ib) in.w #imm8,r0
in.l #imm8,r0

e6 (ib) out.b r0,#imm8

e7 (ib) out.w r0,#imm8
out.l r0,#imm8

e8 (cw) bsr.w label
(cd) bsr.l label

e9 (cw) br.w label
(cd) br.l label

ea (cd) jmp.ww segment:label
(cp) jmp.wl segment:label

eb (cb) br.b label

ec in.b r1,r0

ed in.w r1,r0
in.l r1,r0

ee out.b r0,r1

ef out.w r0,r1
out.l r0,r1

f0 lock

f2 rep_r2 (fuer INS,MOVS,OUTS,LODS,STOS)
repne_r2 (fuer CMPS,SCAS)

f3 rep_r2 (fuer INS,MOVS,OUTS,LODS,STOS)
repeq_r2 (fuer CMPS,SCAS)

f4 halt

f5 bchg.w #0,sr

f6 /0 (ib) tst.b #imm8,ADRS
/2 (ib) not.b ADRS
/3 (ib) neg.b ADRS
/4 mulu.b ADRS,r0,m0|r0
/5 muls.b ADRS,r0,m0|ro
/6 divu.b ADRS,m0|r0
/7 divs.b ADRS,m0|r0

f7 /0 (iw) tst.w #imm16,ADRS
(id) tst.l #imm32,ADRS
/2 (iw) not.w ADRS
(id) not.l ADRS
/3 (iw) neg.w ADRS
(id) neg.l ADRS
/4 mulu.w ADRS,r0,r1|r0
mulu.l ADRS,r0,r1|r0
/5 muls.w ADRS,r0,r1|r0
muls.l ADRS,r0,r1|r0
/6 divu.w ADRS,r0,r1|r0
divu.l ADRS,r0,r1|r0
/7 divs.w ADRS,r0,r1|r0
divs.l ADRS,r0,r1|r0

f8 bclr.w #0,sr

f9 bset.w #0,sr

fa bclr.w #9,sr

fb bset.w #9,sr

fc bclr.w #10,sr

fd bset.w #10,sr

fe /0 inc.b ADRS
/1 dec.b ADRS


ff /0 inc.w ADRS
inc.l ADRS
/1 dec.w ADRS
dec.l ADRS

/2 jsr.w (ADRS)
jsr.l (ADRS)

/3 jsr.ww (ADRS)
jsr.wl (ADRS)

/4 jmp.w (ADRS)
jmp.l (ADRS)

/5 jmp.ww (ADRS)
jmp.wl (ADRS)

/6 move.w ADRS,-(sp)
move.l ADRS,-(sp)




ModR/M fuer 16-Bit Adressierung

| | m0 m2 m1 m3
| Register | r0 r2 r1 r3 r7 r4 r5 r6
| /n | 0 1 2 3 4 5 6 7
-------------------------------------------------------------------------
(r3.w,r5.w) | 00 /n 000 | 00 08 10 18 20 28 30 38
(r3.w,r6.w) | 00 /n 001 | 01 09 11 19 21 29 31 39
(r4.w,r5.w) | 00 /n 010 | 02 0a 12 1a 22 2a 32 3a
(r4.w,r6.w) | 00 /n 011 | 03 0b 13 1b 23 2b 33 3b
(r5.w) | 00 /n 100 | 04 0c 14 1c 24 2c 34 3c
(r6.w) | 00 /n 101 | 05 0d 15 1d 25 2d 35 3d
off.w | 00 /n 110 | 06 0e 16 1e 26 2e 36 3e
(r3.w) | 00 /n 111 | 07 0f 17 1f 27 2f 37 3f
-------------------------------------------------------------------------
off.b(r3.w,r5.w) | 01 /n 000 | 40 48 50 58 60 68 70 78
off.b(r3.w,r6.w) | 01 /n 001 | 41 49 51 59 61 69 71 79
off.b(r4.w,r5.w) | 01 /n 010 | 42 4a 52 5a 62 6a 72 7a
off.b(r4.w,r6.w) | 01 /n 011 | 43 4b 53 5b 63 6b 73 7b
off.b(r5.w) | 01 /n 100 | 44 4c 54 5c 64 6c 74 7c
off.b(r6.w) | 01 /n 101 | 45 4d 55 5d 65 6d 75 7d
off.b(r4.w) | 01 /n 110 | 46 4e 56 5e 66 6e 76 7e
off.b(r3.w) | 01 /n 111 | 47 4f 57 5f 67 6f 77 7f
-------------------------------------------------------------------------
off.w(r3.w,r5.w) | 10 /n 000 | 80 88 90 98 a0 a8 b0 b8
off.w(r3.w,r6.w) | 10 /n 001 | 81 89 91 99 a1 a9 b1 b9
off.w(r4.w,r5.w) | 10 /n 010 | 82 8a 92 9a a2 aa b2 ba
off.w(r4.w,r6.w) | 10 /n 011 | 83 8b 93 9b a3 ab b3 bb
off.w(r5.w) | 10 /n 100 | 84 8c 94 9c a4 ac b4 bc
off.w(r6.w) | 10 /n 101 | 85 8d 95 9d a5 ad b5 bd
off.w(r4.w) | 10 /n 110 | 86 8e 96 9e a6 ae b6 be
off.w(r3.w) | 10 /n 111 | 87 8f 97 9f a7 af b7 bf
-------------------------------------------------------------------------
r0 | 11 /n 000 | c0 c8 d0 d8 e0 e8 f0 f8
r2 | 11 /n 001 | c1 c9 d1 d9 e1 e9 f1 f9
r1 | 11 /n 010 | c2 ca d2 da e2 ea f2 fa
r3 | 11 /n 011 | c3 cb d3 db e3 eb f3 fb
r7 / m0 | 11 /n 100 | c4 cc d4 dc e4 ec f4 fc
r4 / m2 | 11 /n 101 | c5 cd d5 dd e5 ed f5 fd
r5 / m1 | 11 /n 110 | c6 ce d6 de e6 ee f6 fe
r6 / m3 | 11 /n 111 | c7 cf d7 df e7 ef f7 ff
-------------------------------------------------------------------------

Adressierungsarten die (r4.w) bzw. (r4.w,ri.w) enthalten wird uber
s7 adressiert.


=========================================================================


ModR/M fuer 32-Bit Adressierung

| | m0 m2 m1 m3
| Register | r0 r2 r1 r3 r7 r4 r5 r6
| /n | 0 1 2 3 4 5 6 7
-------------------------------------------------------------------------
(r0.l) | 00 /n 000 | 00 08 10 18 20 28 30 38
(r2.l) | 00 /n 001 | 01 09 11 19 21 29 31 39
(r1.l) | 00 /n 010 | 02 0a 12 1a 22 2a 32 3a
(r3.l) | 00 /n 011 | 03 0b 13 1b 23 2b 33 3b
[sib1-byte] | 00 /n 100 | 04 0c 14 1c 24 2c 34 3c
off.l | 00 /n 101 | 05 0d 15 1d 25 2d 35 3d
(r5.l) | 00 /n 110 | 06 0e 16 1e 26 2e 36 3e
(r6.l) | 00 /n 111 | 07 0f 17 1f 27 2f 37 3f
-------------------------------------------------------------------------
off.b(r0.l) | 01 /n 000 | 40 48 50 58 60 68 70 78
off.b(r2.l) | 01 /n 001 | 41 49 51 59 61 69 71 79
off.b(r1.l) | 01 /n 010 | 42 4a 52 5a 62 6a 72 7a
off.b(r3.l) | 01 /n 011 | 43 4b 53 5b 63 6b 73 7b
off.b+[sib2-byte] | 01 /n 100 | 44 4c 54 5c 64 6c 74 7c
off.b(r4.l) | 01 /n 101 | 45 4d 55 5d 65 6d 75 7d
off.b(r5.l) | 01 /n 110 | 46 4e 56 5e 66 6e 76 7e
off.b(r6.l) | 01 /n 111 | 47 4f 57 5f 67 6f 77 7f
-------------------------------------------------------------------------
off.l(r0.l) | 10 /n 000 | 80 88 90 98 a0 a8 b0 b8
off.l(r2.l) | 10 /n 001 | 81 89 91 99 a1 a9 b1 b9
off.l(r1.l) | 10 /n 010 | 82 8a 92 9a a2 aa b2 ba
off.l(r3.l) | 10 /n 011 | 83 8b 93 9b a3 ab b3 bb
off.l+[sib2-byte] | 10 /n 100 | 84 8c 94 9c a4 ac b4 bc
off.l(r4.l) | 10 /n 101 | 85 8d 95 9d a5 ad b5 bd
off.l(r5.l) | 10 /n 110 | 86 8e 96 9e a6 ae b6 be
off.l(r6.l) | 10 /n 111 | 87 8f 97 9f a7 af b7 bf
-------------------------------------------------------------------------
r0 | 11 /n 000 | c0 c8 d0 d8 e0 e8 f0 f8
r2 | 11 /n 001 | c1 c9 d1 d9 e1 e9 f1 f9
r1 | 11 /n 010 | c2 ca d2 da e2 ea f2 fa
r3 | 11 /n 011 | c3 cb d3 db e3 eb f3 fb
r7 / m0 | 11 /n 100 | c4 cc d4 dc e4 ec f4 fc
r4 / m2 | 11 /n 101 | c5 cd d5 dd e5 ed f5 fd
r5 / m1 | 11 /n 110 | c6 ce d6 de e6 ee f6 fe
r6 / m3 | 11 /n 111 | c7 cf d7 df e7 ef f7 ff
-------------------------------------------------------------------------

Adressierungsarten die (r4.l) enthalten, werden ueber s7 adressiert.




sib_byte


Index-Register rk | r0 r2 r1 r3 none r4 r5 r6
/n | 0 1 2 3 4 5 6 7
-------------------------------------------------------------------------
(r0.l,rk.l) | 00 /n 000 | 00 08 10 18 20 28 30 38
(r2.l,rk.l) | 00 /n 001 | 01 09 11 19 21 29 31 39
(r1.l,rk.l) | 00 /n 010 | 02 0a 12 1a 22 2a 32 3a
(r3.l,rk.l) | 00 /n 011 | 03 0b 13 1b 23 2b 33 3b
(r7.l,rk.l) | 00 /n 100 | 04 0c 14 1c 24 2c 34 3c
off32(rk.l) | 00 /n 101 | 05 0d 15 1d 25 2d 35 3d *)
(r4.l,rk.l) | 00 /n 101 | 05 0d 15 1d 25 2d 35 3d **)
(r5.l,rk.l) | 00 /n 110 | 06 0e 16 1e 26 2e 36 3e
(r6.l,rk.l) | 00 /n 111 | 07 0f 17 1f 27 2f 37 3f
-------------------------------------------------------------------------
(r0.l,rk.l*2) | 01 /n 000 | 40 48 50 58 60 68 70 78
(r2.l,rk.l*2) | 01 /n 001 | 41 49 51 59 61 69 71 79
(r1.l,rk.l*2) | 01 /n 010 | 42 4a 52 5a 62 6a 72 7a
(r3.l,rk.l*2) | 01 /n 011 | 43 4b 53 5b 63 6b 73 7b
(r7.l,rk.l*2) | 01 /n 100 | 44 4c 54 5c 64 6c 74 7c
off32(rk.l*2) | 01 /n 100 | 45 4d 55 5d 65 6d 75 7d *)
(r4.l,rk.l*2) | 01 /n 101 | 45 4d 55 5d 65 6d 75 7d **)
(r5.l,rk.l*2) | 01 /n 110 | 46 4e 56 5e 66 6e 76 7e
(r6.l,rk.l*2) | 01 /n 111 | 47 4f 57 5f 67 6f 77 7f
-------------------------------------------------------------------------
(r0.l,rk.l*4) | 10 /n 000 | 80 88 90 98 a0 a8 b0 b8
(r2.l,rk.l*4) | 10 /n 001 | 81 89 91 99 a1 a9 b1 b9
(r1.l,rk.l*4) | 10 /n 010 | 82 8a 92 9a a2 aa b2 ba
(r3.l,rk.l*4) | 10 /n 011 | 83 8b 93 9b a3 ab b3 bb
(r7.l,rk.l*4) | 10 /n 100 | 84 8c 94 9c a4 ac b4 bc
off32(rk.l*4) | 10 /n 101 | 85 8d 95 9d a5 ad b5 bd *)
(r4.l,rk.l*4) | 10 /n 101 | 85 8d 95 9d a5 ad b5 bd **)
(r5.l,rk.l*4) | 10 /n 110 | 86 8e 96 9e a6 ae b6 be
(r6.l,rk.l*4) | 10 /n 111 | 87 8f 97 9f a7 af b7 bf
-------------------------------------------------------------------------
(r0.l,rk.l*8) | 11 /n 000 | c0 c8 d0 d8 e0 e8 f0 f8
(r2.l,rk.l*8) | 11 /n 001 | c1 c9 d1 d9 e1 e9 f1 f9
(r1.l,rk.l*8) | 11 /n 010 | c2 ca d2 da e2 ea f2 fa
(r3.l,rk.l*8) | 11 /n 011 | c3 cb d3 db e3 eb f3 fb
(r7.l,rk.l*8) | 11 /n 100 | c4 cc d4 dc e4 ec f4 fc
off32(rk.l*8) | 11 /n 101 | c5 cd d5 dd e5 ed f5 fd *)
(r4.l,rk.l*8) | 11 /n 101 | c5 cd d5 dd e5 ed f5 fd **)
(r5.l,rk.l*8) | 11 /n 110 | c6 ce d6 de e6 ee f6 fe
(r6.l,rk.l*8) | 11 /n 111 | c7 cf d7 df e7 ef f7 ff
-------------------------------------------------------------------------

Adressierungsarten die als Base-Register (nicht als Indexregister) r4
oder r7 enthalten, werden ueber s7 adressiert.



*) fuer sib1-Byte (MOD=00) kein Base-Register sondern off.l
**) fuer sib2-Byte (MOD=01 oder MOD=10)
.