i8086 architectural fix


Hello!

I was thinking about maybe there
being interest between the intel
assembler programmers and CPU
architecture connoisseurs about
an "unfolded segment:offset"
version of the original i8086.

As every programmer here knows
the 8086 has some redundant bits
in its addressing. Were it would have
managed 16+16 (32bits) addressing
it only did "16+4" (20bits, 12bits of
segment and offset registers overlap)
bein able to reach only 1 MegaByte of
memory.

This was _only_ to spare money and
release a cheaper CPU years ago.
Nowadays this memory limit could
be naturally raised up to 4GB.
The new i8086 could be modernized
to "16b data/32b address" as it was
probably supposed...

The specs would be exactly the same
as the good old 8086, same opcodes,
same registers, nearly same transistor
number, few more pins, and 1 Ghz
of speed (maybe more), ...
but with 16+16=32bits segment:offset
addressing model.

Allowing 4GB of addressable memory
at once, with the power and simplicity of
the genuine, original Intel x86 processor.

The rest remains the same.

OK, thinking further, the classic need
of intel for backwards compatibility
is not fully met. All machine code and
assembled code, would have to be
rewritten? No, using the segment:offset
registers without redundant tricks
makes the code between old and new
8086 portable.
Only programs that use the address
register pairs in a sane way survive
this little architecture fix.

On the other hand this makes the 8086
overall more compatible, forwards
and backwards.


Greetings,
Herman Samso (so_o2@xxxxxxxxxxxx)



[ I am reposting this, as it seems to have
disappeared or someone has interfered.
The posting is not found by google.
I also did some changes/corrections. ]


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