Re: Arithmetic shift right
- From: kaja_love160@xxxxxxxxx
- Date: 26 Mar 2007 12:26:07 -0700
hiya
On Mar 26, 10:47 am, Herbert Kleebauer <k...@xxxxxxxxx> wrote:
kaja_love...@xxxxxxxxx wrote:
Most questions are already answered, but different answers maybe give
different insight.
I'm really sorry for asking so many questions in one single thread,
I suppose you can't ask enough questions so we would get the on topic
post above 1%.
but I don't want to spam this message group with numerous threads. All
my questions are related to Motorola 6803. Could you help me?
1)
Command LSR ( Logical Shift Right ) shifts all the bits by one to the
right. Highest order ( HO ) bit gets value of 0.
Command ASR (Arithmetic Shift Right ) also shifts all bits by one to
the right, but here HO bit gets value of 1.
If you shift a byte right, the only choose you have is, to define
the new value for the highest order bit (the other 7 bits are already
defined by "shift right"). Most CPU's let you choose between four
different ways to define the most significant bit. The bit which is
shifted out from the least significant bit is stored in the Carry
Flag. N and Z flags are set accordingly the result.
1. The most significant bit becomes 0. This instruction is called
"Logical Shift Right". If the value in the byte is interpreted as
an unsigned integer, then the result of the LSR is the old value
divided by 2
2. The most significant bit is not modified. This instruction is
called "Arithmetic Shift Right". If the value in the byte is interpreted
as an signed integer, then the result of the LSR is the old value
divided by 2 (but rounding for negativ values is done to the
next lower value in opposite to most div instructions)
3. The most significant bit becomes the value of the least significant
bit before the shift. This instruction is called "Rotate Right". There
is no arithmetic interpretation for this type of shift. The 6800
doesn't support this type of shift.
4. The most significant bit becomes the value of the Carry Flag.
This instruction is called "Rotate Right Carry". There
is nor arithmetic interpretation for this type of shift. On the
6800 this instruction is called ROR. This instruction can be used
to do multi byte shifts.
My script claims that due to LSR command the value of V flag in CCR
register is set to zero. Which makes sense, since value can't overflow
if we shift its bits by one to the right. But when trying this command
on MC 6800 emulator ( this emulator has quite a few bugs, so this may
be a bug also, but I'm not sure ) V flag was set to 1. Why?
The V Flag doesn't make much sense in the shift instructions. For the
6800 V is defined as: V= N xor C (N,C after the shift). Whether this is
a useful definition is an other question.
Why would ( in shift instructions ) C flag make more sense or be more
of use than V flag? They both alert us that overflow has happen ( C
for unsigned and V for signed numbers )?
3) Branch command BCS branches if carry happens and thus flag C is set
to 1. Couldn't BCS be used as
branch if y < 0, where y = b - a?
I'm asking this cos other branch statements have names like "branch if
greater than ( BGE )" or "branch if higher ( BHI )" ..., but BCS
( branch if carry set ) doesn't have such name, so I'm thinking I'm
missing something obvious.
Most probably your assembler supports two names for the same branch
instruction:
"branch carry clear" or "branch higher same"
"branch carry set" or "branch lower"
After a sub instruction I prefer the "branch carry set" whereas
after a a cmp instruction I use "branch lower". But this is
just a personal preference, sub and cmp do exactly the same
(but cmp doesn't store the result) and also the two branch
instructions are the same.
b)
Similar question for BVS command.
No, that's not similar. A "greater equal" is not V but NV+(~N)(~V) = ~ (N xor V)
So unlike BCC, which is just the other name for command BHS, we don't
have another BVS-like command ( only with different name )? In what
kind of conditional statements can BVS be used?
b)
My script claims that due to LSR command the value of V flag in CCR
register is set to zero. Which makes sense, since value can't overflow
if we shift its bits by one to the right.
No? If we view the number as "signed" (assuming 6803 uses "two's
complement") a "negative" number could become "positive" (the meaning of
"overflow"?) using LSR - might make sense to set the flag(?). If ASR,
there shouldn't be any "overflow"... (I would expect...)
It would make sense to set V flag to 1 if number is viewed as signed.
thank you all for helping me out
.
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