Re: pushf v rcl, save, restore carry flag


stork wrote:

I'm writing my own large integer library in x86-64 assembly, and, to
start with, I'm working on addition. My basic approach is to loop
through each pair of 64 bit longs and adc them. The one thing I've
noticed is that for this to work I need to save and restore the carry
flag, as, my loop counter sets it too. What's the fastest way to do
that these days? I'm looking at pushf, popf, but, some sites that
I've looked at claims rcr/rcl ought to be faster as of 486 and
pentium. Is this still true?

I can only talk on AMDs, Intel CPUs may have this different.

Yes, PUSHF/POPF seem to have the worst timing (vectored 1+?/16).
RCL reg,1 (vectored 7) will beat PUSH/POP by far, but ...
LAHF(vectored 3) and SAHF(direct 1) pairs are faster, but must use AH.
SETcc reg (direct 1) and TEST reg,imm (direct 1) may be the fastest
and can use any available byte register and time almost even to
LAHF/SAHF for SETcc[mem]/TEST[mem] pairs.

At the moment I use LAHF/SAHF for up to 512 bit calculation,
and I think to use SETcc AL/TEST AL,1 pairs for the next upgrade

I'm looking at the AMD64 Architecture guide, Vol 3, and it doesn't
give much about timings at all, although it describes the instructions
reasonably well. Is there a document out there that gives some sort
of an idea of clock ticks for instruction (like the old days), or is
it that today's processors are so massively pipelined that going by a
ticks per instruction isn't going to cut it and you really need to
think in terms of everything else you have going on?

Yes, we are asked to keep many things in mind and are almost lost
when exact timing calculation on x86 code would be required ...

But for a raw estimation of code duration (worst case)
I use the latency/throughput figures from AMD 40546.pdf:
'Software Optimization Guide for AMD Family 10h Processors'
and AMD 25112.pdf:
'Software Optimization Guide for AMD64 Processors'

__
wolfgang



.

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