Re: mov gs, edi - is it safe/supported?


James Harris wrote:
...
Yeah, let the hardware rule our register numbering.

Thanks for all the info. For reference, I've written up a summary of
the info I have from your comments, the reference manuals and, mainly,
assembler (Nasm) output. Hopefully someone will shout if anything
needs to be corrected or something should be added.
Monospaced viewing is recommended!

Let me try if my old eyes can still do it :)

X86/i386 Register Encodings

General registers
-----------------

These follow sequences a-c-d-b and sp-bp-si-di
Code 8-bit 16-bit 32-bit

000 al ax eax
001 cl cx ecx
010 dl dx edx
011 bl bx ebx
100 ah sp esp
101 ch bp ebp
110 dh si esi
111 bh di edi

Yes, and you could add the address-encoding to it:
Code 16-bit |32-bit mod=00 |mod=01 |mod=10

000 DS:[bx+si] DS:[eax] DS:[eax+-disp8] ..+disp32]
001 DS:[bx+di] DS:[ecx] DS:[ecx ..
010 SS:[bp+si] DS:[edx] DS:[edx ..
011 SS:[bp+di] DS:[ebx] DS:[ebx ..
100 DS:[si] SIB present SIB present SIB present
101 DS:[di] DS:[imm32] SS:[ebp+-disp8] ..+disp32]
110 DS:[imm16] DS:[esi] DS:[esi+-disp8 ..+disp32]
111 DS:[bx] DS:[edi] DS:[edi..

in general we may see x86-code as octal grouped
|mod|r/m|reg| or |11|reg|reg| or |mod|ttt|r/m| or ...
And just to add to the confusion :) if SIB is present:
|scale|index|base| where the base will change for:

mod=00 |mod=01 |mod=10 (all mod from SIB)
100 SS:[esp+idx] SS:[esp+idx+disp8] SS:[esp+idx+disp32]
101 DS;[imm32+idx] SS:[ebp+idx+disp8[ SS:[ebp+idx+disp32]

scaled index-registers again follow the 32-bit order,
EXCEPT:
100 "No Index" ;esp cannot be an scaled index-register


Segment registers
-----------------

These follow separate sequences: e-c-s-d and f-g

Code Push/Pop/Seg-Override

00 es
01 cs
10 ss
11 ds

0 fs
1 gs


Push/pop segment register encoding can be seen in these where the
binary represents the last opcode byte:

06 000 00 11p push/pop es
0e 000 01 11p push/pop cs
16 000 10 11p push/pop ss
1e 000 11 11p push/pop ds

0fa0 1010 0 00p push fs
0fa8 1010 1 00p push gs

The 'p' at the end is 0 = push, 1 = pop.

Right.

Segment overrides follow the same e-c-s-d and f-g sequcences:

26 001 00 110 es:
2e 001 01 110 cs:
36 001 10 110 ss:
3e 001 11 110 ds:

64 0110010 0 fs:
65 0110010 1 gs:

Load far pointer
----------------

Load far pointer instructions do not follow the above rules,
apparently having been fitted in whereever there was space and bearing
in mind that a far load of CS was not valid and would not need an
encoding. The binary that follows represents the last opcode byte in
each case.

Opcode Binary Instruction
c4 1100010 0 les
c5 1100010 1 lds
0fb2 10110010 lss (no reg encoding as such)
0fb3 10110011 (BTR, _not_ a far pointer load)
0fb4 1011010 0 lfs
0fb5 1011010 1 lgs

Yes, and with shift/and its easy to build segreg-Numbers 0..5
for all case above.
I have one single printed page out of an Intel book (page 2-6,
but can't remember which one), a usefull quick-view reference.

__
wolfgang





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