Re: announce: my very first disassembler now available (GPL)

On Aug 16, 8:59 pm, Willow <wrschlan...@xxxxxxxxx> wrote:
The latest version is here:http://code.google.com/p/vm64dec/downloads/list

I think those size problems are fixed now. Here is a list of known
erratta:

1. It never prints "near". This is the default so it shouldn't matter.
2. aad, aam have an argument. This is actually valid.
3. xchg needs to be turned into nop when applicable. Need to do this!

There's also a special case in 64-bit mode. Depending on the rex
prefix (AFAIR, bit B) it can be either NOP or XCHG.

4. Need to add support for extended opcodes such as 'd9 f4' (fxtract)
and '66 0f 38 01' (phaddw). How to do this? Do any extended opcodes
have a modr/m? Can we pretend the opcode byte is an immediate byte?

Normally, almost every instruction that has mod<3 has a memory operand
(some exceptions: 3dNow! instructions have a dummy memory operand (as
well as some multibyte NOP instructions) and MOV CR/DR according to
the documentation ignore mod). Instructions that have an opcode
extension in the reg field (denoted as /number) can have the following
operands according to the ModR/M byte value (there may be implicit,
non-ModR/M ones, too):
- register AND register/memory, e.g. ADD
- memory AND register, e.g. BOUND
- memory OR register, e.g. LTR
- memory only, e.g. XRSTOR
- none, e.g. LFENCE, VMCALL

FPU instructions are generally encoded the same way as non-FPU
instructions if there's a memory operand (i.e. mod<3). The same is
often true about FPU instructions that don't have a memory operand,
but not always. E.g. there's FSTSW AX that seems to be valid/existent
only for AX and the r/m field often denotes not some register but a
particular instruction (i.e. further extends the opcode), e.g. F2XM1
through FCOS.

Alex
.

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