Re: NASM 0.98.39 vs. NASM 2.03.01 disassembly

On Aug 19, 6:24 am, "Rod Pemberton" <do_not_h...@xxxxxxxxxxxxx> wrote:
"Nathan Baker" <Nat...@xxxxxxxx> wrote in message

news:g8des6$3ct$1@xxxxxxxxxxx

Frank Kotler wrote:
Given the presentation of the instruction decode lines and the 8/16
and 8/32
etc. register separation of the cpu,

I really question this!

Me too.

"Executable code segment. The flag is called the D flag and it indicates the
default length for effective addresses and operands referenced by
instructions in the segment. If the flag is set, 32-bit addresses and 32-bit
or 8-bit operands are assumed; if it is clear, 16-bit addresses and 16-bit
or 8-bit operands are assumed."

IA-32 Intel(R) Architecture Software Developer's Manual Volume 3A:System
Programming Guide, Part 1, pg 3-14, 2006

Mixed mode programming (i.e., overrides) is one way to change the
operational operand and address sizes, but this doesn't change the way the
instructions are *encoded*, as 8/16 or 8/32 etc.


So, is "movzx eax, mem16" really a 16-bit instruction using a 32-bit
override; or is it a 32-bit instruction which is doing two 8-bit moves
simultaneously??

Nathan.
.

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