Re: NASM 0.98.39 vs. NASM 2.03.01 disassembly

Rod Pemberton wrote:
"Frank Kotler" <fbkotler@xxxxxxxxxxx> wrote in message

The source is 16 bits...

Where's your proof? Nasm64developer said so?

Viktor: "Lucian is dead."
Singe: "According to whom?"

Intel/AMD define the processor architecture, including the
instruction set and opcode map. But the symbolic representation
of an instruction is not defined by the processor architecture
(and therefore not by Intel/AMD) but by the author of the assembler.
This symbolic representation should be as logic as possible (which
therefore excludes the use of the symbolic representation used by
Intel/AMD in the processor manuals).

Now, a selector has a size of 16 bit. So if you have to specify
a register which holds the selector, it's "logical" to use the name
of a 16 bit register (lsl eax, bx) and not a 32 bit register name
(lsl eax, ebx).

But even more logical it would be, to put the size to the
instruction and not to the register;

ldsl.l r3,r0


It's the same as with the shift instruction. You use

"shl eax,cl" and not "shl eax,ecx" because cl better
fits to the 5 bit shift count than ecx. But also here
the logical way would be:

lsl.l r2,r0
.

Relevant Pages

  • Re: Intel illogical syntax...
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  • Re: How does this make you feel?
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  • Re: Designing my own architecture to be simulated in software - need help with the ISA
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  • Re: How does this make you feel?
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  • Designing my own architecture to be simulated in software - need help with the ISA
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    (comp.arch)