Re: NASM 0.98.39 vs. NASM 2.03.01 disassembly

On Thu, 21 Aug 2008 02:50:31 -0400
"Rod Pemberton" <do_not_have@xxxxxxxxxxxxx> wrote:

But, to me, it seems that the
opcode map fails to make much sense for source register disassembly
for LAR and LSL by not fitting the cpu's register model.

True enough, but what you refer to as the "register model" doesn't
make much sense either. Even in the emulated IA-32 hardware model,
there are no 8-bit or 16-bit registers. And in the x86_64 model,
there are no 32-bit registers. When we refer to the "AH register",
for example, what we really mean is the low order 8 bits of the EAX
register. [Or in my case, the low order 8 bits of the RAX register.)
Nevertheless, the notation is useful, because it clearly indicates the
number of bits affected. Thus, it makes sense to me to disassemble a
register operand which Intel specifies as Ew as a 16-bit register.

As to the opcode map, for many years now, Intel has been walking a
tight-wire between the desire to take advantage of new technology
and the industry demand for machine level compatibility. As a result,
the opcode map has long since lost all resemblance to the actual
hardware. Today's actual cpu register model is an implementation
dependent number of 128-bit registers, with the move to 256-bit
registers promised in the next year or two.

The NASM team, having pretty much gotten its act together with respect
to the x86_64 architecture and its associated REX prefixes, is now
learning to cope with the 128-bit and 256-bit AVX extensions and their
associated VEX prefixes.

Is it any wonder then that none of us are particularly concerned about
conforming to a register model which is now a quarter-century old?

--
Chuck
http://www.pacificsites.com/~ccrayne/charles.html


.

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  • Re: NASM 0.98.39 vs. NASM 2.03.01 disassembly
    ... for LAR and LSL by not fitting the cpu's register model. ... but what you refer to as the "register model" doesn't ... used to encode an instruction, a 16-bit instruction can encode only two ... register operand which Intel specifies as Ew as a 16-bit register. ...
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