Re: NASM 0.98.39 vs. NASM 2.03.01 disassembly

"Chuck Crayne" <ccrayne@xxxxxxxxxx> wrote in message
news:20080822155808.79b62eb3@xxxxxxxxxxxxxxxxxx
On Fri, 22 Aug 2008 04:10:42 -0400
"Rod Pemberton" <do_not_have@xxxxxxxxxxxxx> wrote:

I'm not sure why you used "emulated" in this sentence...

[snip CISC via RISC]

In other words, the cpu is a super-scalar RISC-like engine wrapped in a
layer of microcode which emulates the earlier x86 processors.

(Since you said "RISC-like", I won't start in on you or Gabriel Torres
indicating that the later Pentiums core qualify as RISC... I'll use
"RISC-ish" so you know what I'm referring to although that's not correct
either...)

I don't usually refer to that as "emulation". Emulation, to me, implies a
system which can't execute the code natively. A CISC cpu using a "RISC-ish"
core can execute the instructions natively as CISC. It can't execute
anything user provided on the "RISC-ish" core. It can only execute
translated or converted to "RISC-ish" instructions from CISC instructions on
the "RISC-ish" core. So, I tend to think of this as translation,
conversion, etc.


RP

.

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