Re: NASM 0.98.39 vs. NASM 2.03.01 disassembly



Chuck Crayne <ccrayne@xxxxxxxxxx> wrote in part:
In my view, true RISC has been dead for many years now. The original
RISC concept was that by supporting only a few basic instructions,
it would be possible to execute one instruction in each machine
cycle. A goal which, of course, has long since been surpassed.

Yes, but was extended by parallel execution -- RISC cores went
quad-issue long ago while x86 still is stuck at triple issue,
possibly due to flag dependencies.

Unfortunately, however, RISC became more of a marketing
term than a technical one,

I would dispute the "unfortunately". As I see it, IA64 (Itanium)
was a logical development of RISC and had it been possible to make
it succeed, Intel would have. It was not, because adaptive dynamic
hardware (like ROB) cannot be replaced by static software (compiler
scheduling). This compiler failure is indirectly positive for ASM.

That said, RISC is far from dead. ARM is RISC and owns the
low-power market. To the extent computing is heat/power-limited,
ARM++ may make a place in server farms and compute clusters.
Linux & NetBSD (at least) are available as full environments.
Only the hardware (MB cache, quad core 3 GHz ARMs) is lacking.

and I still know a number of otherwise highly respected computer
professionals who commonly use RISC as a synonym for Unix.

LOL!

The point remains, however, that the P6 had 40 80-bit registers,
and a register renaming routine which allowed [e.g.] multiple EAX
registers containing different values to be in existence at any
one time.

Indeed. CPU developement has been very incremental since the 10
year old iP6 and aK6 cores. AFAICS, the basic triple-issue ROB,
dispatch and retirement are unchanged. Rename registers and other
buffers have been added with some execution engines and increased
pipelineability. Even 64 is just width and decode. Nothing like
the transition from the dual-issue iP5 (original Pentium/MMX).


-- Robert

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