Re: [NEWBIE] i686 architecture

From: Matt Taylor (para_at_tampabay.rr.com)
Date: 12/13/03 

Date: Sat, 13 Dec 2003 20:44:41 +0000 (UTC)

"Mariusz 'Craig' Cieśla" <craig_@_aristocracy.pl> wrote in message
news:pan.2003.12.13.16.55.24.316755@_aristocracy.pl...
> Hello,
>
> I'm a newbie in assembly coding on Intel i686 family (I coded only on
> Zilog's Z-80 uP and 8051 uC, some coding on 8086 uP). Can you give me some
> interesting docs about i686? You know - registers, structure, memory
> access (I've heard it's half-RISC architecture, whatever it means, I only
> met with RISC and CISC architectures), stack etc.

Half-RISC means that Intel's P6 family (Pentium Pro, Pentium 2, Pentium 3)
have a RISC-like core. On the front of the processor there are x86 decoders
which take CISC x86 instructions and convert them into an internal format
which Intel calls micro-ops. The micro-ops are then dispatched to execution
units. K6/K6-2/K6-3, Athlon, and Pentium 4 all use this strategy as well.

You can get all the information you need out of the Intel IA-32 manuals:
http://www.intel.com/design/Pentium4/manuals/index.htm

Though those manuals are for the Pentium 4, the architecture is largely the
same. Volume 2 is a reference on the opcode format, but it also includes a
thorough description of the entire instruction set.

I would also recommend sitting down with a compiler, writing some C code,
and looking at its output. Many x86 features are painfully obvious once you
see an example.

To get you started, x86 has 8 registers:
eax - accumulator reg; usually encodes shorter than other instructions; used
in multiplies, divides, string ops, and cbw/cwde/cwd/cdq instructions
ebx - base pointer; used implicitly by xlat
ecx - counter; used in loop, jecxz, and rep prefixed instructions
edx - paired with eax for multiply and divide
esi - source index; used implicitly in string instructions
edi - destination index; used implicitly in string instructions
ebp - frame pointer; no architecturally specific function
esp - stack pointer; used implicitly by push/pop, call, & ret instructions

In 32-bit code, any register can be used in a general-purpose fashion. Some
registers are still used implicitly by certain instructions, but most of
these old CISC instructions aren't used. Memory addressing is more complex
than in RISC architectures. It follows the form [base+index*scale+offset]
where base is any register, index is any register except esp, scale is 1, 2,
4, or 8, and offset is an immediate.

-Matt

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