Prescott Disappoints

From: Matt Taylor (para_at_tampabay.rr.com)
Date: 02/17/04 

Date: Tue, 17 Feb 2004 07:07:35 +0000 (UTC)

We all know that Prescott got a shifter and multiplier, and there were a
number of overhauls to the core. I was poking through the latest Intel
Optimization Manuals, and I am absolutely shocked. Here are a number of
downsides:

1. Multiplies still suck. They were 14-18 cycles before; now they're 10
cycles, and in some cases they aren't any faster. Since shifts are 1 cycle
now, you might as well emulate most constant multiplies.
2. No more double-speed ALU ops. I can't get a straight answer here, but all
of the ALU ops went from 0.5 clk latency/throughput to 1 clk. This means
that one of the key advantages was cut. I don't know if this means the ALUs
are no longer running double-speed, though I have heard this claimed.
3. New horizontal add instructions are useless. With a throughput of 4
cycles and latency of 13, it is faster to use shuffle + add.
4. Increased latencies of floating-point instructions. All adds/multiplies
are now 1 cycle (20%) slower. Likewise some of the mux instructions
(minps/maxps) and the conversion instructions are a cycle slower.
5. Slower L1 dcache (50%!)

What advantages does Prescott have? Well, they made a few less common
instructions encode in the u-op cache, and shifts/rotates are now 1 cycle.
All of the advantages are minor tweaks; seems to me they broke more
important stuff in the process.

-Matt

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