Re: What's the purpose of the instruction 'int 03' ?

From: Matt Taylor (para_at_tampabay.rr.com)
Date: 03/10/04 

Date: Wed, 10 Mar 2004 08:10:57 +0000 (UTC)

"sugaray" <ruicui@sohu.com> wrote in message
news:ad3defeb.0403092235.87a4bab@posting.google.com...
> hi, i noticed in disassemblers like IDA, between each function body
> there are bunch of instruction 'int 03', can sombody tell me what
> are their purposes ? thanx.

Cache line alignment. You want to start functions and loops on a cache line
in order to minimize the amount of memory the CPU has to load in the event
of a cache miss.

-Matt

Relevant Pages

  • Re: Self function
    ... those in the function body itself? ... function that uses a cache, while still keeping around the version ...     return f ... This still has the memoizing problem. ...
    (comp.lang.python)
  • Re: [BUG] slab debug vs. L1 alignement
    ... Perhaps we should remind ourselves what the alignment rules actually are ... No two kmalloc allocations may share cache lines (otherwise data ... architecture. ...
    (Linux-Kernel)
  • Re: Byte alignment
    ... I was told by one client who is using high-end Xeons that even the 32-bit chipsets are now ... optimizing cache hits for regular computations during my system programming course. ... 64-byte alignment. ... and they are very unhappy with their nVidia-based motherboards. ...
    (microsoft.public.vc.mfc)
  • Re: reading a text file into a string
    ... If you are buffering lines and want to avoid unintentional cache ... support specified Alignments that are greater than the maximum Alignment ... This applies to subtypes, ...
    (comp.lang.ada)
  • Re: [rfc][patch 3/3] use SLAB_ALIGN_SMP
    ... I dont understand why you added SLAB_SMP_ALIGN, without removing SLAB_HWCACHE_ALIGN on these places. ... alignment on UP systems as well because we care about the layout of the ... While HWCACHE_ALIGN might be a hint saying: ... The writer carefully designed the structure so that max performance is obtained when all objects starts on a cache line boundary, ...
    (Linux-Kernel)