x86 architecture questions
From: ziliath (ziliath_at_myway.com)
Date: 03/23/04
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Date: Tue, 23 Mar 2004 22:33:49 +0000 (UTC)
Hi all,
I've been dealving into the glory-and-gore that is the x86
architecture, and I have a few questions for the gurus...
1. Is there a way to have paging on for some tasks and
off for others? I want some fixed-size processes to enjoy
the greater speed of never paging. To put it differently,
can the paging-on flag be set and cleared at will by a kernel?
2. What compilers support 36-bit addressing? Or, if the systems
on which my kernel will run have only 32 lines wired up, can you think
of any risk in enabling 32-bit addressing anyway? (I want to
use 2-MB pages.)
3. Dumb question: can a privilege level 0 tasks (a kernel)
easily access the data of level 1/2/3 tasks ?
I am trying to figure out why Unix/Linux are supposedly
notorious for copying data instead of using pointers, if that
makes sense.
4. Which privilege levels are normally assigned to user-space tasks
on the x86? Is multithreading typically accomplished at level 3,
with apps at level 2? How does Hyperthreading complicate the picture?
5. Let's say that hypothetically, my OS will use only the 4 or 2
meg pages, never 4kB. Is there a way to ensure that the TLB
will not be invalidated with every task switch? I'm under the
impression that invalidation is automatic.
I hope these questions didn't seem too dim... I've only just
begun plowing through the Intel manuals.
Thanks,
Z
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