Re: The Linear Address Space
From: Heck (heck_at_toodamnmuchspambutreallycomputer.org)
Date: 04/27/04
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Date: Tue, 27 Apr 2004 17:56:35 +0000 (UTC)
""Cameron Gibbs" <odly@hotmail.com>" draws inspiration from a reality most
only suspect:
>Hey people.
>
>I have been working through the IA-32 Software Developer's Manuals. I have
>read pretty much all of it in some detail (skipping mostly just tables and
>lists that can be referenced as needed). Still there is something very basic
>in my understanding that is lacking.
>
>There is a Physical Address Space of 4GBytes (2^32 bytes) which basically
>identifies all of the binary numbers that can be used as addresses for
>assembly language programming.
>With the 36-bit address extensions it is possible to increase this to
>64Gbytes.
>The problem is that in a computer there is Hard Drive storage, RAM storage
>and a heap of other devices and the like that all require byte addresses.
>Say for example you had a 180GByte HDD in your system, even with the 36 bit
>address extension mechanisms which bring the Physical Address Space up to
>64GBytes, there are still just not enough Logical Addresses to reference the
>whole of the addresses on a system.
>
>Also with Hard Drive partitions and with every program having to be put in a
>particular spot on the Hard Drive, it is a very rare thing that one would
>write a program that is to be put at address zero.
>>>From all this I have come to think that the Linear Address Space is simply
>an abstraction or a virtualization of the true state of all of the addresses
>within a computer so what I need to know is how are these abstractions that
>are used in a program "mapped" to the real addresses of the computer?
>How does this work?
>
>Also, I think that paging has something to do with RAM management and the
>"checking in" and "checking out" of data to and from RAM but frankly I can
>neither confirm nor deny this and hence I just cannot figure out what is
>actually going on with paging.
>Am I on the right track with paging? - Please correct!
>
>Might the mapping to real addresses have something to do with the Page
>Directory Base Register (PDBR) which is Control Register 3 (CR3)?
>
>All help appreciated.
>
>Cameron.
The physical address space are all the addresses the processor can use,
correct. None of the other potential addresses are mapped or recognized
by the processor in any way, however, they can be used if they are paged
in. Just as with any conventional packing problem, bringing something in
necessitates swapping something out. Segment registers hold the offsets
into the total available pool of storage.
Read chapter 3 again, and, in particular, 3-4, in the System Programmer's
Guide.
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