Re: About MMX\SSE2 PSADBW instruction ?

From: Ivan Korotkov (koroNOSPAMtkov2_at_ztelDOT.ru)
Date: 05/06/04 

Date: Thu, 6 May 2004 17:52:08 +0000 (UTC)

> 2) the main size is 1024 char array....But i don't undertsand why the mod
> 4096 addresses of pvec1 and pvec2 could get performance penalties ?

Cache is thrashed. On your CPU, L2 should be 8-way associative, thus it can
contain up to 8 64-byte lines with the same 12 LSB's. Frequent moves between
such addresses can degrade performance because cache has to be reloaded
frequently.

Ivan

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