Re: Xeon and Events

From: Grumble (a_at_b.c)
Date: 06/07/04 

Date: Mon, 7 Jun 2004 17:59:08 +0000 (UTC)

Christian Lande wrote:

> may be I'm wrong but it seems that it measures only µops-misses
> not data misses?

What do you call a µop-miss?

NetBurst does not implement a traditional L1 instruction cache.
Instead it has a so-called trace cache.

Thus, when the Intel documentation mentions "the number of retired µops
that experienced 1st-Level cache load misses", I believe it must refer
to the data cache.

You could ask Mikael Pettersson, he added support for the PMCs in Linux.

His documentation mentions:

   The following command counts the number of L1 cache read misses
   on a Pentium 4 processor:

   [snip]

   Explanation: IQ_CCCR0 is bound to CRU_ESCR2, CRU_ESCR2 is set up
   for replay_event with non-bogus uops and CPL>0, and PEBS_ENABLE
   and PEBS_MATRIX_VERT are set up for the 1stL_cache_load_miss_retired
   metric. Note that bit 25 is NOT set in PEBS_ENABLE.

http://archive.ncsa.uiuc.edu/lists/perftools/jan04/msg00001.html

I suppose you could try and see for yourself :-)

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