Re: piplining principles (and confusion!)
From: Bob Masta (NoSpam_at_daqarta.com)
Date: 09/07/04
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Date: Tue, 7 Sep 2004 12:19:52 +0000 (UTC)
On a related issue:
In the "good old days" we could use self-modifying code
to tell an 8088 from an 80286 by modifying an opcode
just ahead of the current instruction. If it was an 8088
with a short queue, the modification would be done
before the modified instruction was read, and it would
thus be acted upon. If it was an 80286, the target
instruction was already in the queue and so the
original form was acted upon, and the mod ignored.
In general, if you were doing self-modifying code and
did *not* want the "queue trap", you could insert a
jump before the target, which would flush the queue
and assure that the changed code was acted upon.
So, my question is how all this relates to modern
pipeline and cache operation. Are all modern
CPUs smart enough to recognize that a write is
going to change an instruction already in the pipeline,
and flush it? If not, what are the rules for safe
self-modifying code?
Thanks!
Bob Masta
dqatechATdaqartaDOTcom
D A Q A R T A
Data AcQuisition And Real-Time Analysis
www.daqarta.com
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