Re: Bit extraction

From: Ross A. Finlayson (spamtrap_at_crayne.org)
Date: 09/19/04 

Date: Sun, 19 Sep 2004 18:20:01 +0000 (UTC)

>
> ?
>

The register EAX has its low 16 bits being AX, where AX has high byte
AH and low byte AL.

Because the low byte of your packed integers contains the low two
nybbles where their size sums to eight, I think you can use the fact
the AX is by itself (AH << 8) | AL.

Then, I forgot to shift right the operands. So I think the idea is
that starting with input in EAX, to copy it into EBX, and then if each
number was four bits instead of the last two being three and two it
would be easier.

So:

POP AX ; put input into AX
NOP ; pair prev.
MOV BX, AX ; copy AX to BX
NOP ; pair prev.
AND AX 0000_0111_0000_1111b ; mask AH and AL
AND BX 0001_1000_1111_0000b ; mask BH and BL
SHR BX, 3 ; shift BX right
SHR BL; shift BL right

I think the NOP goes in place to allow it to pair with the instruction
preceding it. That is because the following instruction will pair
with its next instruction, but not its previous one. The NOP always
pairs with the previous instruction if it is a pairable instruction in
the right pipeline on the Pentium. Maybe that means that the NOP is
actually useless because if an instruction doesn't pair with its
previous and can with its next that it will, I don't know. The main
pipeline is the U pipeline, if the next instruction has no side
effects on the operands and working data of the U pipeline, and is a
simple (one byte) instruction, then it is executed in parallel in the
V pipeline on the superscalar Pentium Pro+, each is prefetched in the
U pipeline, although I don't know much about that, there are basically
in terms of Pentiums the Pentium, Pentium MMX, Pentium Pro, Pentium
II, Pentium III, or Pentium 4. Other chips implementing the x86
instructions are manufactured by AMD, Cyrix, and others. Where NOP is
implemented as MOV EAX, EAX, then it does not pair with other
instructions affecting EAX.

The return value of a function that returns byte, short, or long is
stored in eax. A floating point value is returned in st(0), which is
an 80-bit floating point register. I don't really understand how many
stacks the function has available. I think it has a stack available
for the data segment. There are the ebp register and eip registers,
each contains a pointer, eip should not be capriciously modified, ebp
should be not different than it was when the function began on return.

If the function definition in C is along the lines of:

getStructBits(unsigned int input, unsigned int* pa, unsigned int* pb,
unsigned int* pc, unsigned int* pd)

then I think where the a, b, c, and d values are in resp. al, ah, bl,
bh, then you pop the pointers off the stack and then move the values
into the memory at those addresses.

POP CX
POP DX
MOV [CX], AL
MOV [DX], AH
POP CX
POP DX
MOV [CX], BL
MOV [DX], BH

I think my code is incorrect as I am still quite lacking understanding
assembler. The variables should be in order on the argument list thus
that they are popped off the stack in a reasonable order for their
use. I'd like to learn more about alignment issues.

?

Does anybody happen to have a table or tables of the clock and cycle
counts of each supported instruction on each x86 processor? I've seen
them in separate documents and am hoping someone has already correctly
transcribed them into XML or some other tractable data representation.

Regards,

Ross F.

Relevant Pages

  • VMI Interface Proposal Documentation for I386, Part 5
    ... to three register arguments. ... of the native instruction set. ... Most of these calls behave as standard C functions, and as such, may ... clobber registers EAX, EDX, ECX, flags. ...
    (Linux-Kernel)
  • Re: 8-Bit Register on Pentium 4
    ... or later) do not have MOVZX instruction nor MOVSX instruction. ... Please look at Pentium 4 Optimization on page 76. ... It's only the dependency issues (which we ... >> register, but not AH, BH, CH, and DH registers. ...
    (comp.lang.asm.x86)
  • x86 stack-frame to stack-frame move
    ... one stack-frame location to another? ... mov eax ... to some virtual scratch register. ... So I suppose my question is this: can I expect recent x86 instruction ...
    (comp.lang.asm.x86)
  • Re: An Object-Oriented Syntax for x86 Assembly
    ... Ok, this is probably better, or easier, then thrashing a register. ... > second operand that specifies the size. ... I'd expect that one to read from EAX only, ... > which would be exactly the same instruction as above, ...
    (alt.lang.asm)
  • MOVZX has stall register
    ... It is very interesting that I want to mention why MOVZX would have ... EAX, EAX. ... It makes the processor into thinking that this register is truly ... 32 bits register plus it has to use AND instruction to mask only 8 ...
    (comp.lang.asm.x86)