Re: math co-processor exceptions

From: Scott J. McCaughrin (spamtrap_at_crayne.org)
Date: 10/19/04 

Date: Tue, 19 Oct 2004 03:44:55 +0000 (UTC)

Chewy509 <spamtrap@crayne.org> wrote:
: "Scott J. McCaughrin" wrote in message...
: > This is a follow-up to elaborate upon my previous post. With
: > the low-order 6 exception bits masked off (P,U,O,Z,D,I = 0),
: > it would seem that when an exception is detected, a handler
: > should be invoked for it.
: > E.g., sqrt(-1.0) does turn on the Z exception bit in the
: > status word (setting ES as well), but no handler is invoked.
: >
: > Do I need to send data out some port to enable interrupts?
: >

: Maybe be a stupid question, but what have you set the current exception
: handler to? masked or unmasked? Sounds like your running in masked mode.

: --
: Darran (aka Chewy509)...

Darran:

All 6 exception bits are unmasked in the control word. To test this, I
have created test conditions to raise all 6 exceptions, and each does
show up in the status word as being set. As I noted in my example, the
example of sqrt(-1.0) turns on the (unmasked) I (Invalid) flag (sorry
I mislabeled it Z (Zero-divide)!).

I have handlers installed at INT 02h and INT 75 (the latter does some
preliminary work, then forwards its task to INT 02h). There are a few
complexities with the NMI handler at INT 02: it has to distinguish
between an FWAIT and ESC raising the exception, but my problem is that
I never see either ISR invoked. Must I check the status word after every
operation and manually invoke these handlers via INT calls? Aren't these
co-processor exceptions supposed to automatically trigger interrupts, the
way integer-divide overflow triggers the INT 0 handler automatically?

The debugger I use is x87-friendly and shows all the flags raised when
the pertinent conditions occur, but I am also checking all 6 bits in
the lower half of the NPX status word as well.

-- Scott

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