Branch/load delay in x86 architecture?

From: Erik Larsson (spamtrap_at_crayne.org)
Date: 10/24/04 

Date: Sun, 24 Oct 2004 18:02:26 +0000 (UTC)

I've been doing a little assembly programming earlier in life, but mostly
with RISC-architectures. Now I'm learning x86... and I wonder about some
things I learned back then:
Does one have to consider load delay/branch delay in the Intel-architecture?
Because from the programming examples I've seen, it doesn't really look that
way.
>>From what I've learned load/branch delay was a result of the processor using
pipelining, and the pipeline on intel I've heard from somewhere, has up to
15 steps or so?
Are there any other things one has to consider when writing Intel assembly
code? Similar problems?
  Erik

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