Re: math co-processor exceptions

From: Chewy509 (spamtrap_at_crayne.org)
Date: 10/25/04

  • Next message: Mark Gibson : "Re: Branch/load delay in x86 architecture?" 
    Date: Mon, 25 Oct 2004 08:22:27 +0000 (UTC)

    "Scott J. McCaughrin" wrote in message...
    > Chewy509 wrote:
    > : Hi Scott,
    >
    > : One of the other things I forgot to mention. What's the value of the NE
    > flag
    > : in CR0? (bit 5 of CR0)
    >
    > : If it's 1, then you in Native Mode, which invokes Int 16d (#MF
    > exception).
    >
    > : But if NE is set to 0 in CR0, then your in MS-DOS compatibility mode, in
    > : which case your Int75h handler should be invoked, assuming that the mask
    > : bits are set correctly (which no doubt they are). (At least according
    > to
    > : Section 8 and Appendix D of Volume 1 of the IA-32 architecture manuals).
    >
    > That is correct. I have tried both modes, with the same result: neither
    > INT 10h in Native Mode nor INT 75h in DOS Mode are getting invoked.
    >
    > Thanks for the references.

    I suggest that you reread those references I gave, but what environment are
    you running this code in? ie under Linux, Windows, DOS, straight from a
    Bootsector, within an emulator (VMWare, Bochs, emu8086, or other), within a
    debugger?

    This is really bizarre? (Insights from others would be appreciated).

    What chip are you running this on? Have you reprogrammed the APIC or PICs in
    any manner before your running your code? Also have you had a look at the
    initial environment that you are given before code execution? (It may
    provide a clue, to what's going on)? 

    -- 
Darran (aka Chewy509)...
  • Next message: Mark Gibson : "Re: Branch/load delay in x86 architecture?"

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