Re: Branch/load delay in x86 architecture?

From: Betov (spamtrap_at_crayne.org)
Date: 10/25/04 

Date: Mon, 25 Oct 2004 17:26:27 +0000 (UTC)

"Erik Larsson" <spamtrap@crayne.org> écrivait
news:WGLed.6937$d5.58788@newsb.telia.net:

> I've been doing a little assembly programming earlier in life, but
> mostly with RISC-architectures. Now I'm learning x86... and I wonder
> about some things I learned back then:
> Does one have to consider load delay/branch delay in the
> Intel-architecture? Because from the programming examples I've seen,
> it doesn't really look that way.
>>>From what I've learned load/branch delay was a result of the processor
>>using
> pipelining, and the pipeline on intel I've heard from somewhere, has
> up to 15 steps or so?
> Are there any other things one has to consider when writing Intel
> assembly code? Similar problems?

You will get two types of answers to these questions:

1) The answers from programmers who never wrote anything
significative, in Assembly, and that will push you to
eventually consider these points.

2) The answers from programmers who write full Assembly
Applications, currently. These ones will tell you that
Assembly is very simple to write, and that all of the
Code Level Optimisations Tips&Tricks should be fermely
rejected, unless very exceptional cases, that you do
not have to consider, for a start.

My answer is: No, you do not have to consider these
things, and no, there is no such similar problem to be
considered. I have written the fastest of the actual
PE Assemblers - 2.7 Megas of Asm Sources - and i never
took any care of doing any Code Level Optimisation. The
only things, that matter, are Readibility, and Strategy
Optimisation).

Betov.

< http://rosasm.org/ >

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