Re: Does Linux hog fs and gs registers?
From: kingzog (spamtrap_at_crayne.org)
Date: 02/10/05
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Date: Thu, 10 Feb 2005 22:42:25 +0000 (UTC)
Dan wrote:
> We all lament the limited number of registers on the x86, so it is
> disappointing that Windows reserves fs and gs for itself. I'm
> considering jumping ship and going to Linux.
>
> Does Linux hog fs and gs? Is there some way under Windows to get
> around this? Is there some good reason to do this, given the design
of
> the chip?
I don't know about Linux, but in Windows FS points to the Thread
Enviroment block, which contains things like the exception handler and
thread local storage. I don't know about GS. On other platforms like
Alpha a register is still dedicated to this. On x86 FS is a good
choice, since it is a segment register and is thus very slow to load in
protected mode, but since the TEB pointer only changes on a context
switch it's not a problem. The other reason it can be used is that 32
bit code normally only uses the CS and DS segments, the default
segments for code and data respectivley. In Windows user mode code,
these both have a base address of 0 and a limit of 4GB, which means
that you can access all user memory with a 32bit offset from them.
There really isn't much reason to use the other segment registers.
Microsoft have decided to 'document' the TEB here -
http://msdn.microsoft.com/library/default.asp?url=/library/en-us/dllproc/base/teb.asp
Of course, NTDDK.H in the device driver kit contains a fuller
definition as describe in this excellent Matt Pietrek article here
http://www.microsoft.com/msj/archive/S2CE.aspx
Oh, and this idea of using FS to point to the TEB is one of the few
examples of a hardware being changed to support software.
In the original proposal for AMD64, all the segment base and limit
registers would be ignored in 64 bit mode. Since code generated by a
Windows C++ compiler contains code to access hardwired offsets off FS
to do exception handling, this would need major changes to Windows. The
current, shipping AMD64 chips ignore CS and DS base and limit, but
implement the FS and GS base correctly.
It's not a bad compromise, presumably 90% instructions will use the
default segment registers, and so the address generation can skip a
uop. Only instructions with a segment override prefix to FS or GS need
to have the extra addition to implement the segment base and even there
the segment limits are all ignored. So AMD implements just enough
segmentation to allow Windows code to use FS as the TEB pointer without
compromising much on performance.
>
> Thanks for any insight you have to this problem.
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