Re: iA32 Paging
- From: Jack Klein <jackklein@xxxxxxxxxxx>
- Date: Sat, 4 Jun 2005 05:02:55 +0000 (UTC)
On Fri, 3 Jun 2005 17:20:00 +0000 (UTC), "Richard Harris"
<spamtrap@xxxxxxxxxx> wrote in comp.lang.asm.x86:
> Hi,
> I am trying to implement paging on IA32 processors.
> Here is what I think I know:
>
> A Virtual Address is split up into 3 parts
>
> 10 bits | 10 bits | 12 bits
> Page Dir Page Frame Offset
If you are going to draw ASCII diagrams, make sure you use a fixed
point font, otherwise they might not line up on the reader's screen.
> The high ten bits are used to index into the page directory 0-1023
> and the next ten bits index into the page frame 0-1023 and the offset
> just gives the offset into the page.
>
> My problem is with the page directory and page frame data entries.
> Each entry is 32 bits and the high 20 bits are the base address for both
> and the low 12 bits are used for parameters like is present etc.
>
> Why do these entries have 20 bits ie ( 20 + 20 bits = 40 bits ). Surely you
> only need 10 bits for each entry to give you the 10 + 10 + 12 bits for the
> physical address ?
>
> How do I set the physical address in place in the page directory and page
> frame data entries?
>
> Any help on understanding this would be most helpfull
>
> Thanks people!
None of the bits in the 20-bit address field in the page directory
entry has anything to do with the physical address.
It works like this:
10 bits | 10 bits | 12 bits
Page Dir Offset | Page Table Offset | Offset
The top 10 bits in the linear address select one of 1,024 entries in
the page directory table. The high 20 bits of physical address of the
page directory are in the CR3 register.
The 20 bit address in the page directory entry is the physical address
of a page table. Each page table starts on an address that is evenly
divisible by 4096. The 10 bit Page Table Offset from the linear
address selects one of the 1,024 entries in the page table.
The 20 bit address in the page table entry form the top 20 bits of the
physical address. Combined with the 12 bit offset in the linear
address, they make the full 32 bit address of a byte within the 4,096
byte page.
So the page directory table has 1,024 entries, each of which can point
to a page table. Each page table has 1,024 entries, each of which
points to a page. Each page has 4,096 bytes.
So if you use all possible page directory and page table entries, you
have 1,204 x 1,024 pages of 4,096 bytes each, which is exactly the
size of the full 32-bit, 4 gig linear address space.
--
Jack Klein
Home: http://JK-Technology.Com
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