Re: Combining two MMX registers into one SSE register?

Wow great news. I already had resigned to the fact not to use MMX under
w64:

Some quotes
----------------------------------------------------------------
http://www.amd.com/us-en/assets/content_type/DownloadableAssets/dwamd_AMD64_Porting_FAQ.pdf
page 11 (May 2003)

Floating-point calculations in AMD64
Can x87 instructions still be used by 64-bit applications?

64-bit applications cannot use x87 instructions because 64-bit
operating systems are not required to preserve the x87 stack across
interrupts and context switches. AMD has gone to great lengths to
ensure that SSE/SSE2 math library performance and accuracy exceeds that
of the x87 instruction set. We anticipate no need to use x87
instructions in 64-bit applications.

----------------------------------------------------------------

http://www.amd.com/us-en/assets/content_type/DownloadableAssets/dwamd_Porting_Win_DD_to_AMD64_Sept24.pdf
page 7 (Sepetember 2003)

Convert media instruction to SSE/SSE2 Instructions

Microsoft Windows for AMD64 will not context switch x87, 3Dnow!, MMX
for 64-bit native threads.
This code may be converted to SSE/SSE2 through the use of intrinsic
functions-

----------------------------------------------------------------
http://www.freepascal.org/wiki/index.php/Win64/AMD64_API#Data_type_sizes

Notes on Win64 for AMD calling conventions

About x87 and mmx registers

x87 and mmx registers aren't used: all floating points calculations are
made in XMM* registers. Although x87 and mmx registers are guaranteed
to be preserved across context switching, this is not true for
functions calls. Microsoft says that if you use x87 registers you
should consider them as volatile registers. There's nothing about mmx
registers apart the context-switching thing, so I think that even mmx
registers have to be considered volatile.

----------------------------------------------------------------
http://www.agner.org/assem/calling_conventions.pdf

6.1 Can floating point registers be used in 64-bit Windows?

There is widespread confusion about whether 64-bit Windows allows the
use of the floating point registers ST(0)-ST(7) and the MM0 - MM7
registers that are aliased upon these. One early technical document
found at Microsoft's website says "x87/MMX registers are unavailable to
Native Windows64 applications" (Rich Brunner: Technical Details Of
Microsoft® Windows® For The AMD64 Platform, Dec. 2003). An AMD
document says: "64-bit Microsoft Windows does not strongly support MMX
and 3Dnow! instruction sets in the 64-bit native mode" (Porting and
Optimizing Multimedia Codecs for AMD64 architecture on Microsoft®
Windows®, July 21, 2004). A document in Microsoft's MSDN says: "A
caller must also handle the following issues when calling a callee:
[...] Legacy Floating-Point Support: The MMX and floating-point stack
registers (MM0-MM7/ST0-ST7) are volatile. That is, these legacy
floating-point stack registers do not have their state preserved across
context switches" (MSDN: Kernel-Mode Driver Architecture: Windows DDK:
Other Calling Convention Process Issues. Preliminary, June 14, 2004;
February 18, 2005).

This description is nonsense because it confuses saving registers
across function calls and saving registers across context switches.
Some versions of the Microsoft assembler ml64 (e.g. v. 8.00.40310)
gives the following message when attempts are made to use floating
point registers in 64 bit mode: "error A2222: x87 and MMX instructions
disallowed; legacy FP state not saved in Win64".

However, a public discussion forum quotes the following answers from
Microsoft engineers regarding this issue: "From: Program Manager in
Visual C++ Group, Sent: Thursday, May 26, 2005 10:38 AM. It does
preserve the state. It's the DDK page that has stale information, which
I've requested it to be changed. Let them know that the OS does
preserve state of x87 and MMX registers on context switches." and
"From: Software Engineer in Windows Kernel Group, Sent: Thursday, May
26, 2005 11:06 AM. For user threads the state of legacy floating point
is preserved at context switch. But it is not true for kernel threads.
Kernel mode drivers can not use legacy floating point instructions."
(www.planetamd64.com/index.php?showtopic=3458&st=100).

The issue has finally been resolved with the long overdue publication
of a more detailed ABI for x64 Windows in the form of a document
entitled "x64 Software Conventions", well hidden in the bin directory
(not the help directory) of some compiler packages. This document says:
"The MMX and floating-point stack registers (MM0-MM7/ST0-ST7) are
preserved across context switches. There is no explicit calling
convention for these registers. The use of these registers is strictly
prohibited in kernel mode code." My tests indicate that these registers
are saved correctly during task switches and thread switches in 64-bit
mode, even in an early beta version of x64 Windows. Furthermore, I see
no reason to not save these registers. If the floating point registers
were not saved during a task switch then they would have to be cleared
for security reasons; and the time required for clearing these
registers would be no less than the time required for saving these
registers. The floating point registers must be supported when running
legacy 32-bit programs as well. These considerations do not apply to
kernel mode where information security is less of an issue. According
to the above information, the operating system may not save the
floating point registers across kernel mode context switches.

The Microsoft C++ compiler version 14.0 never uses these registers in
64-bit mode, and doesn't support long double precision. The Intel C++
compiler for x64 Windows supports long double precision and __m64 in
version 9.0 and later, while earlier versions do not.

The conclusion is that it is safe to use floating point registers and
MMX registers in 64-bit Windows, except in kernel mode drivers.


.

Relevant Pages

  • Re: builtin lists and Intel SSE support?
    ... However the floating point speedups could also be related to the ... > utilising extra integer registers). ... > ability to intermix integer and floating-point instructions in the same ... > This achieves potentially four times the computational work of x87 ...
    (comp.lang.lisp)
  • Re: MMX instructions and floating point stack
    ... > floating point arithmetic. ... the FPU stack are also the MMX registers. ... So if I load ST0 with 1.0, then issue an MMX instruction, the entire ...
    (comp.lang.asm.x86)
  • Re: performance gain with 32 bit Linux on 64 bit system
    ... I will have a 32 bit Linux running on ... Floating Point has been processed 64bits at a time for a very very long ... added a bunch of additional registers which are only available to a 64 ... Generally if the data set is mostly 32 integers and it's large but not so ...
    (comp.os.linux.misc)
  • Re: performance gain with 32 bit Linux on 64 bit system
    ... I will have a 32 bit Linux running on ... Floating Point has been processed 64bits at a time for a very very long ... added a bunch of additional registers which are only available to a 64 ... Generally if the data set is mostly 32 integers and it's large but not so ...
    (comp.os.linux.misc)
  • Re: CPU for Compaq Fortran V 6.4
    ... >The original MMX was designed for multimedia, ... >compilers generated code to do it from without any help. ... >and restore its registers. ... real kind (floating point) variables with 32 bits. ...
    (comp.lang.fortran)