Re: CISC vs RISC concepts -- from an assembly view

HellsRaison <spamtrap@xxxxxxxxxx> wrote in part:
And RISC CPUs rely their speed on _compiler_ optimizations
(converting the least amount of operations done with what
the user is trying accomplish.

Yep, that's the theory.

So if this is true, shouldn't everyone be using RISC processors
and just use really smart compilers to create their executable.
Because that way the RISC can go extremely fast (1:1 ratio
of CPU Cycles : Operations -- or at least close to this), and

Modern CPUs are multiple issue -- more than one op per clock.
Orig Pentium and Pentium4 (under many circumstances), two.
PentiumPro/II/III/M (P6) and AMD K6/K7/K8: three max.
Later Alphas, etc: four. And later x86 CPUs really are RISC
internally -- the CISC instructions are translated.

Am I thinking clearly and realistically?

Not worse than Intel when they promoted their IA64 (Itamium)
RISC architecture :) Who knows how many billions that cost them!
And they should've known from their i860 and iAPX432 RISC debacles.

I'm not sure of all the problems, but I believe compiler
technology simply didn't deliver. And perhaps couldn't.
Many algorithms are chaotic (data driven). The hardware renamers
and instruction schedulers inside P6/K6+ do a pretty good job
of reordering/scheduling instructions on-the-fly. Better than
a static compile, it appears.

-- Robert

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Relevant Pages

  • Re: IBM 45nm -- new or licensed from Intel?
    ... However this increases power consumption for all fetches, ... all instructions). ... I had the impression that 2-way for a RISC was 1 general integer FU ... x86compilers for lower-end, embedded systems?) ...
    (comp.arch)
  • Re: 32 or even 64 registers for x86-64?
    ... instructions to do the same thing as CISC, ... Today's RISC CPUs don't have a minimized set of instructions. ...
    (comp.arch)
  • Re: Are 80x86 badly designed processors ?
    ... That's because old compilers were unable to deal with such big number of ... registers the RISC has. ... deals with 8 specialised registers rather than 32 general-purpose. ... Do you prefer a CPU with 32-bit instructions? ...
    (comp.lang.asm.x86)
  • Re: 32 or even 64 registers for x86-64?
    ... instructions to do the same thing as CISC, ... Today's RISC CPUs don't have a minimized set of instructions. ...
    (comp.arch)
  • Re: 32 or even 64 registers for x86-64?
    ... Today's RISC CPUs don't have a minimized set of instructions. ... did HP call Spectrum a RISC architecture? ...
    (comp.arch)