Re: CISC vs RISC concepts -- from an assembly view
- From: "toby" <spamtrap@xxxxxxxxxx>
- Date: 25 Apr 2006 09:09:47 -0700
HellsRaison wrote:
Now this question just popped out of my head. I'm viewing this as a C
program to an x86 assembly output.
CISC CPU speed is relied on microprocessor optimizations (like 3DNow!
and MMX, SSE2, SSE3 extensions/optimizations) which are enabled by the
compiler.
And RISC CPUs rely their speed on _compiler_ optimizations (converting
the least amount of operations done with what the user is trying
accomplish.
So if this is true, shouldn't everyone be using RISC processors and
just use really smart compilers to create their executable. Because
that way the RISC can go extremely fast (1:1 ratio of CPU Cycles :
Operations -- or at least close to this), and all of the advanced math
stuff (that Intel uses -- SSE2, SSE3) would be embedded within the
executable output.
Am I thinking clearly and realistically?
I recommend Hennessy & Patterson, "Computer Architecture: A
Quantitative Approach," for a survey of the topic:
http://dogbert.abebooks.com/servlet/SearchResults?sts=t&an=hennessy&tn=architecture
.
- References:
- CISC vs RISC concepts -- from an assembly view
- From: HellsRaison
- CISC vs RISC concepts -- from an assembly view
- Prev by Date: Re: CISC vs RISC concepts -- from an assembly view
- Next by Date: Re: CPU identification
- Previous by thread: Re: CISC vs RISC concepts -- from an assembly view
- Next by thread: Re: CISC vs RISC concepts -- from an assembly view
- Index(es):
Relevant Pages
|