Re: CISC vs RISC concepts -- from an assembly view


"Tim Roberts" <spamtrap@xxxxxxxxxx> wrote in message
news:v6er42d8r5jc8gv0lfq8b51a6iaskdura0@xxxxxxxxxx
"HellsRaison" <spamtrap@xxxxxxxxxx> wrote:

So if this is true, shouldn't everyone be using RISC processors and
just use really smart compilers to create their executable. Because
that way the RISC can go extremely fast (1:1 ratio of CPU Cycles :
Operations -- or at least close to this), and all of the advanced math
stuff (that Intel uses -- SSE2, SSE3) would be embedded within the
executable output.

Am I thinking clearly and realistically?

Not quite. The theory is that a single CISC instruction can get more done
than a single RISC instruction. In a pure "1 cycle" RISC computer, the
instruction set cannot include instructions which require more than one
cycle. For example, many pure RISC processors do not even have a divide
instruction. The divide has to be simulated in software.

If RISC were unconditionally better than CISC, you would have seen the
CISC
processors evaporate. That has not happened.

The RISC processors ran faster, instructions were simple, and most executed
in a single clock. IIRC, the problem was that the simple instructions
created massive code bloat. This required large amounts of very fast memory
and caches to keep the processor fed with instructions. Unfortunately, fast
memory during the CISC vs. RISC period was expensive. This effectively
killed RISC, IMO. CISC cpu's took a memory is expensive, therefore we shall
conserve memory approach. This was done with a higher 'code density' (more
powerful instructions per amount memory used) and layers of "cache"
(registers, L1, L2, main memory) . As memory has cheapened and as the speed
of main memory approaches that of the cpu caches, you can see (and will see,
I think) a slight shift in the Intel instruction set away from CISC to more
RISC like instructions.


Rod Pemberton


.

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