Re: CISC vs RISC concepts -- from an assembly view

HellsRaison wrote:
Now this question just popped out of my head. I'm viewing this as a C
program to an x86 assembly output.

CISC CPU speed is relied on microprocessor optimizations (like 3DNow!
and MMX, SSE2, SSE3 extensions/optimizations) which are enabled by the
compiler.

And RISC CPUs rely their speed on _compiler_ optimizations (converting
the least amount of operations done with what the user is trying
accomplish.

So if this is true, shouldn't everyone be using RISC processors and
just use really smart compilers to create their executable. Because
that way the RISC can go extremely fast (1:1 ratio of CPU Cycles :
Operations -- or at least close to this), and all of the advanced math
stuff (that Intel uses -- SSE2, SSE3) would be embedded within the
executable output.

Am I thinking clearly and realistically?


Just my $.02...

RISC is better, hands down. CISC is winning in the PC market because CISC chips have become so cheap.

In the late 1970s and early '80s, IBM decided to use Intel chips in their first PCs, mostly because Intel agreed to allow other vendors (AMD and Cyrix/VIA) to produce compatible chips. This gave IBM a feeling of security that even if Intel went out of business, there would still be x86 chips to be had at a reasonable price. Because of the sheer quantity of x86 chips sold for home use, the price dropped drastically, so CISC is what most home users have.

The battle is really not over, though. Consider:

- XBox uses RISC:
http://www.wired.com/news/games/0,2101,61065,00.html

- So does PlayStation:
http://www.us.playstation.com/pressreleases.aspx?id=252

- RISC, especially PowerPC, is still typically used in
high-end servers.

- Modern x86 chips effectively include RISC back ends,
with microcode doing dynamic translation from the
x86 instruction set. As RISC chips continue to
shrink, x86 won't be able to keep up, because so
much of each core has to be wasted on the decoder.

- Even Intel tried to start moving the burden from the
microcode to the compiler by introducing a VLIW
architecture for Itanic.

Of course, Apple recently switched to Intel hardware, so maybe I'm just out of the loop. :)

.

Relevant Pages

  • Re: CISC vs RISC concepts -- from an assembly view
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  • Re: non load/store architecture?
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