Re: CISC vs RISC concepts -- from an assembly view
- From: Jerry Coffin <spamtrap@xxxxxxxxxx>
- Date: Wed, 26 Apr 2006 23:10:51 -0600
In article <H2K3g.5395$P65.4875@xxxxxxxxxxxxxxxx>,
spamtrap@xxxxxxxxxx says...
[ ... ]
The battle is really not over, though. Consider:
Actually, the battle really IS over -- RISC lost a long
time ago. Despite names and claims to the contrary, the
reality is that there's virtually nothing left on the
market that should be called a RISC at all. The early
MIPS processors were at least close, but the recent ones
have instruction sets that are larger and more complex
than (for one example) the 8086.
- XBox uses RISC:
Count up the PowerPC instructions, and then look at the
complexity of some of the Altivec instructions.
The PowerPC is a RISC in name only. If the name RISC had
never been invented, the PowerPC wouldn't have stuck out
as being particularly unusual in any way at all.
- So does PlayStation:
See above.
- RISC, especially PowerPC, is still typically used in
high-end servers.
IBM sells servers based on the POWER series of
processors, that's true. They certainly have high enough
prices that they _should_ be high-end, but to the extent
that they're fast at all, it's because they simply throw
lots of money at the problem, not because of any
superiority to the basic design (which isn't surprising,
since it's not really RISC anyway).
- Modern x86 chips effectively include RISC back ends,
with microcode doing dynamic translation from the
x86 instruction set. As RISC chips continue to
shrink, x86 won't be able to keep up, because so
much of each core has to be wasted on the decoder.
Trying to claim that the x86 is really a RISC internally
is mostly marketing nonsense. By this standard, RISC
never existed at all (since, of course, all microcoded
machines translated from the external instruction set to
microcode that the hardware could execute directly --
that's the basic definition of what microcode IS after
all.
- Even Intel tried to start moving the burden from the
microcode to the compiler by introducing a VLIW
architecture for Itanic.
Yes, and it's failed miserably in the marketplace.
According to the myths, as a more or less RISC chip, it
should be small and simple and burn less power than a
CISC. The reality is that the current Itaniums are some
of the biggest, most complex, most power-hungry chips on
the planet. They're fast for some things, but only
because they're built on a cost-no-object basis. They
include lots of floating-point resources, huge caches,
etc. These work, but in spite of, not because of, the
degree to which the chip qualifies are RISC-like.
--
Later,
Jerry.
The universe is a figment of its own imagination.
.
- References:
- CISC vs RISC concepts -- from an assembly view
- From: HellsRaison
- Re: CISC vs RISC concepts -- from an assembly view
- From: Jeffrey Schwab
- CISC vs RISC concepts -- from an assembly view
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