Re: enabling x87 interrupts
- From: "Rod Pemberton" <spamtrap@xxxxxxxxxx>
- Date: Sat, 26 Aug 2006 12:43:21 -0400
"Scott J. McCaughrin" <spamtrap@xxxxxxxxxx> wrote in message
news:ecnvna$s6c$3@xxxxxxxxxxxxxxxxxxxxxxxxxx
Rod Pemberton <spamtrap@xxxxxxxxxx> wrote:#2
: "Alexei A. Frounze" <spamtrap@xxxxxxxxxx> wrote in message
: news:9tGdnYy8o5tcxnPZnZ2dnUVZ_sadnZ2d@xxxxxxxxxxxxxx
: > Wendy E. McCaughrin wrote:
: > > Is the 8259A (PIC) still used to enable interrupts? I unmasked bit
: > > in the master PIC and bit #5 (a.k.a. #13) in the slave PIC itcascades
: > > with, to enable FPU interrupts. I have unmasked all 6 exceptions in
: > > the FPU's control-word and use STI. Yet, INT 75h is never accessed.
: >
I'm not familiar with the FPU, so I'm not completely sure of everything you
need to do, but I think these should be done:
*1) RM (not V86), so CR0.NE is 0 (initial CR0 is 60000010h)
*2) cli - disable interrupts
3) program master PIC: base address default is 0x08, tell master that slave
is on IRQ2, or use BIOS/DOS defaults
4) program slave PIC: base address default is 0x70, tell slave that IRQ9 is
redirected IRQ2 from master, or use BIOS/DOS defaults
5) mask all unused interrupts both PICs. If using BIOS/DOS defaults, other
interrupts will be triggered
*6) unmask bit 2 master PIC
*7) unmask bit 5 slave PIC
*8) unmask 6 exceptions in FPU control word
9) decide on EOI control: Auto-EOI, non-specific EOI, or specific EOI
*10) setup int 75h handler, using chosen EOI method
11) setup int 10h handler, using chosen EOI method (verify not a cpu
exception, i.e., CR0.NE=1)
12) setup int 0Ah handler, using chosen EOI method (called for 70h to 78h)
13) clearing higher priority interrupts, depending on PIC EOI, or disable
them. If other interrupts are enabled, this will need to be done
continuously as soon as you 'sti'.
*14) sti - enable interrupts
15) must generate an FPU #FERR/#MF by using a "waiting FPU instruction, or
by a MMX instruction," not a non-waiting instruction.
* indicates what you said you've done already.
As you can see from 9), the standard cascaded interrupts calls int 0Ah for
int 70h to 78h. So, how you setup and clear EOIs is important: Auto-EOI,
non-specific EOI, or specific EOI. Depending on how you handle EOIs, int
0Ah can be setup to handle int 75h (clearing both 0Ah and 75h EOIs and
calling int 75h) or not (clear 0Ah EOIs only). If there is an existing int
0Ah handler, i.e., DOS or BIOS, it may be "interfering" if it's handling int
75h directly or clearing the EOI for int 75h...
Rod Pemberton
.
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