Re: Why do Intel's processors provide four debug registers rather than only one?
- From: "robertwessel2@xxxxxxxxx" <spamtrap@xxxxxxxxxx>
- Date: 23 Sep 2006 21:31:06 -0700
Lighter wrote:
Why do Intel's processors provide four debug registers rather than only
one?
As we know, there are four debug registers (DR0 through DR3) inside
every Intel's processor except for the very early ones. What makes me
confused is as follows:
To my thinking, one debug regiter is enough to set a breakpoint for a
runnning program. If we need to set more breakpoints for this program,
we can do this job in the service routine of the debug interrupt. For
example, assuming we want to set two breakpoints at address 5 and 7. To
this end, we can first set DR0 to addess 5, when the program attempts
to executes the instruction at address 5, a debug interrupt will be
triggered and the ISR we provided in advance will be called. In the
ISR, we can set D0 to address 7 and return. Thus, the program will be
interrupted again when it attempts to execute the instruction at
address 7.
Following the steps I describe above seems a good solution to debugging
all kinds of programs. Why does the processor provide four ones? I
cannot think out how much we can benefit from providing more than one
debug register.
What makes you think that the program will execute the instruction at 5
before the instruction at 7 (ignoring the fact the locations "5" and
"7" are unrealistically close together)? Or that it won't execute the
instruction at one location several times before hitting the
instruction at the other location?
In addition, the breakpoints registers can be use to trap different
types of events. For example, a breakpoint register can be set to trap
when data is written to a location, or if an instruction is executed at
that location.
.
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