Re: Branch prediction

On Feb 26, 8:24 am, Muscipula <spamt...@xxxxxxxxxx> wrote:
There is something that is confusing about what I understand about
branch prediction. If the processor is reading ahead of the program
counter then it must be emulating the instructions at least and I find
that unusual.

Please correct me if I have got this right. But from what I know, when
the x86 processor is seeking ahead and reaches a branch it has a
problem. That is it doesn't know what the outcome of the condition
until the program counter gets there.

So, it emulates both paths from the branch until the program counter
gets there. When the processor is seeking ahead/emulating the future
instructions, what exactly is it doing with the code - p-code or
whatever.

There aint much documentation on processors these days like there used
to years back. Even Wikipedia does not have much to say.

I have a registered copy of A386 that I intend to use soon, but my
knowledge of 386> is not much. Can anybody recommend a book, something
like the equivalent of the 8086 book.


Try the Intel docs, including the optimization guides - there's a lot
of information there. In addition, there are bunches of white papers
online describing internals.

Anyway, processors that speculatively execute instructions usually
just follow one path. At conditional branches, they try to predict,
usually based on history or some static information, which way the
branch will go. If they guess wrong, some mechanism undoes the
incorrectly speculated instructions, and the process back itself up to
the point where the incorrect prediction was made and starts again.
That usually involves a hefty performance penalty, so a good (IOW,
rarely incorrect) branch predictor is important.

It's not really that the CPU is emulating any instructions, it's just
trying to execute more of them, and all sorts of things are done to
allow a nominally sequential stream of instructions to execute in
parallel. For example register renaming to eliminate sequential
dependencies, etc. For example, the CPU might detect that it can
issue the next three add instructions in a row all in parallel, since
they don't conflict. Obviously a conditional branch presents a
barrier to that sort of thing, unless you can predict which way the
branch is going to go. And since you can't (usually) predict that
with 100% certainty, the CPU has to be able to back out a bad guess.

The exact mechanisms vary considerably, but most commonly CPUs prevent
committing any results to memory that might need to be undone (many
ISAs, including x86, make that a requirement), so any "false" state is
contained within the processor.

.

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