Re: Structure size directives

Ben Pfaff wrote:
Tor Rustad <tor_rustad@xxxxxxxxxxx> writes:

Ben Pfaff wrote:
Tor Rustad <tor_rustad@xxxxxxxxxxx> writes:

Like I have stated elsewhere, alignment faults will typically be fixed
(at a cost) by the kernel on Windows/x86, but not so, on Windows/MIPS
or Windows/x64.
This is a strange statement. On x86 and x86-64, the CPU does not
raise a fault at all for most kinds of misaligned arguments, in
the operating mode usually used, typically at minimal cost. And
modern versions of Windows do not run on MIPS, except for Windows
CE (which is not usually just called "Windows").
Not so strange, if you consider the Windows DDK doc:

"On 32-bit Windows platforms, the operating system automatically fixes
kernel-mode memory alignment faults and makes them invisible to the
application. [...]

Then it's Microsoft who is making the strange statement.

Well, I find your statement stranger. :) Both IA-64 and AMD64, can be controlled by a kernel to raise exceptions on alignment bugs. When Microsoft state that this is what Windows might be doing, I see no reason to believe otherwise.

> From Intel's documentation for the x86:
>
> 4.1.1. Alignment of Words, Doublewords, Quadwords, and
> Double Quadwords
>
> Words, doublewords, and quadwords do not need to be
> aligned in memory on natural boundaries.

Here is what Intel say in "Itanium Architecture Software Developer’s Manual Volume 2: System Architecture Rev. 2.2":

3.3.2 Processor Status Register (PSR)

[...]

"Alignment Check – When 1, all unaligned data memory references result in an Unaligned Data Reference fault. When 0, unaligned data memory references may or may not result in a Unaligned Data Reference fault."

[...]

"For IA-32 instructions, if PSR.ac is 1 an unaligned IA-32 data memory reference raises an IA_32_Exception(AlignmentCheck) fault."

[...]

4.5 Memory Datum Alignment and Atomicity

"An aligned ld16 or st16 instruction is performed as an atomic 16-byte memory reference. For these instructions, the address specified must be 16-byte aligned. Unaligned ld16 and st16 instructions result in an Unaligned Data Reference fault regardless of the state of PSR.ac."

[...]

"When PSR.ac is 1, any Itanium data memory reference that is not aligned on a boundary the size of the operand results in an Unaligned Data Reference fault; e.g., 1, 2, 4, 8, 10, and 16-byte datums should be aligned on 1, 2, 4, 8, 16, and 16-byte boundaries respectively to avoid generation of an Unaligned Data Reference fault."


> And from AMD's documentation for x86-64:
>
> 3.2.4 Data Alignment
>
> ...The x86-64 architecture does not impose data-alignment
> requirements for accessing data in memory.

Regardning AMD, the "AMD64 Architecture Programmer’s Manual Volume 2: System Programming. Pub. #24593":

"Alignment Mask (AM) Bit. Bit 18. Software enables automatic alignment checking by setting the AM bit to 1 when eFLAGS.AC=1. Alignment checking can be disabled by clearing either AM or eFLAGS.AC to 0. When automatic alignment checking is enabled and CPL=3, a memory reference to an unaligned operand causes an alignment-check exception (#AC)."

--
Tor <bwzcab@xxxxxxxxx | tr i-za-h a-z>
.

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