Re: Version after Version

"Bruce Roberts" <dontsendtober@xxxxxxxxxxxxxxxxxxxx> wrote in message
news:rXR7f.6988$ki7.397918@xxxxxxxxxxxxxxxxxxxxxxxx
[...]
> In days of old the native word size of a cpu indicated the bus width.
> Its not so straightforward in modern architectures. Actually, IIRC,
> an early example of this breakdown was the 80186 which had an 8-bit
> bus and a 16-bit cpu.

The 8086 and 80186 were accompanied by the 8088 and 80188, which saved
everybody money by halving the data bus. (There was an MC68008 along
the same lines.)

The 80286 did not offer this option. It was reinstated with the 80386
where it was called SX (as opposed to DX). This also reduced the
address bus from 32 to 24 bits. With the 80486, the designation SX
was reinterpreted to mean it lacked a built-in floating point
coprocessor.

The 386 also introduced demultiplexing of the lower bits of the address
bus. It did not have A0 and A1 lines, but four "strobe" lines which
told the memory interface which bytes in every 32-bits memory access it
was really interested in. I _think_ the 486 had the same arrangement;
the Pentium demultiplexed one more bit. This didn't match the CPU's
word size, but it did match the L1 cache width.


> I don't think one can assume that a 64-bit cpu is going to load
> 64-bits in a single cycle, even if we are talking about L1 cache.

Nothing much happens in a single cycle anymore, but I would be very
disappointed with a first-level cache that allowed that much latency.
It is, after all, an acceleration device, the first line after the
registers.

Groetjes,
Maarten Wiltink


.

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