Potential FastCode speed increase?

Is any FastCoder using these yet?

<quote IA-32 Intel Architecture Software Developer Manual Volume 1>
11.4.5. Branch Hints
SSE2 extensions designates two instruction prefixes (2EH and 3EH) to
provide branch hints to the processor (see ?Instruction Prefixes? in
Chapter 2 of the IA-32 Intel Architecture Software Developer?s Manual,
Volume 2A). These prefixes can only be used with the Jcc instruction and
only at the machine code level (that is, there are no mnemonics for the
branch hints).
</quote>

<quote IA-32 Intel Architecture Software Developer Manual Volume 2A>
Branch hint prefixes (2EH, 3EH) allow a program to give a hint to the
processor about the most likely code path for a branch. Use these
prefixes only with conditional branch instructions (Jcc).
Other use of branch hint prefixes and/or other undefined opcodes with
IA-32 instructions is reserved; such use may cause unpredictable
behavior.
</quote>

If not this might be a potential speed increase for many functions.
Unfortunately Intel doesn't define a mnemonic for these prefixes, but
of course we could also use DB. We might also put a QC request for
creating mnemonics (unless they are already there in D2005?) in next
versions of Delphi.

.

Relevant Pages

  • Re: Question about Instruction Format (ModR/M)
    ... (the first three bytes, being prefixes, could be in any order) ... This is a 32-bit PM instruction executing in 16-bit RM/PM due to ... they have to push the extra byte back onto the disassembly stream. ...
    (alt.lang.asm)
  • Re: bit representation of assembler commands
    ... the tables in Appendix A translate from opcodes into assembly ... Chapter 3 translates mneumonics into opcodes. ... Redundant prefixes do not change the decoded instruction ... The maximum instruction length is 15 bytes. ...
    (comp.lang.asm.x86)
  • Re: Problem in understanding OpSiz (66h) and ArgSiz (67h) prefixes.
    ... >> for the following instruction only. ... modes are toggled if the 66/67 prefixes respectively are present. ... 2E0000 mov, al ... Redundant prefixes accumulate: ...
    (comp.lang.asm.x86)
  • Re: A valid number of prefixes
    ... AMD manuals say there are 5 classes. ... You've demonstrated knowing the Intel manuals. ... Instruction Prefixes ...
    (comp.lang.asm.x86)
  • Re: Question about Instruction Format (ModR/M)
    ... with the format of a x86 Instruction. ... situation where you'd even reach 10 bytes on a 286 w/o redundant prefixes) ... The prefix-bytes are reserved and cannot be an opcode. ... The SIB byte isn't for 16-bit instructions. ...
    (alt.lang.asm)