Re: something I came to think about ... (logical operators in if statements)
From: David Reeve (dree4456_at_big-pond.net.au)
Date: 11/18/03
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Date: Tue, 18 Nov 2003 06:17:29 GMT
"Maarten Wiltink" <maarten@kittensandcats.net> wrote in message
news:3fb8c77c$0$58702$e4fe514c@news.xs4all.nl...
> "Martin Harvey (Demon Account)" <martin@pergolesi.demon.co.uk> wrote in
> message news:5gcgrvsuab3d5srbtifqfq15oh351aks97@4ax.com...
> [...]
> > [Verilog, a hardware description languages is] Very neat, but you
> > have to be careful if you're a software programmer - the apparent
> > "sequentiality" is of course false - although you can tell it which
> > bits you want clocked, and which bits you don't.
>
> SEQ
> x=y
> y=x
The context is sufficient to resolve the ambiguity. If we declare x and y as
dflops, then this is a recirculating shift register. On every clock edge
whats in x will move to y and vice versa.
> PAR
> x=y
> y=x
>
Whatever form of asynchronous logic we use for x and y, I reckon the
compiler will squawk.
Dave
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