Re: Precision PWM in microcontroller

From: Thad Smith (thadsmith_at_acm.org)
Date: 12/29/03 

Date: Mon, 29 Dec 2003 13:32:31 -0700

Ville Voipio wrote:
>
> Thad Smith <thad@ionsky.com> writes:
>
> > Are you wanting to generate different frequencies? If so, an external
> > Direct Digital Synthesizer (DDS) will do what you want. These can be
> > programmed to generate an accurate frequency. They require an
> > external reference frequency.
>
> In case of a uC, this is easy to do in s/w.

<code snipped>

Good point. I should have thought of that. The tradeoffs between hw/sw
are basically low cost vs. low jitter.

> Making a software DDS is simple, but there are a few things
> which have to be taken into account:
>
> - While the frequency and duty cycle accuracy in the long run
> is extremely good, there is a lot of jitter due to the limited
> sampling frequency. A single cycle may have a very bad duty
> cycle (1:2 in the worst case). RMS jitter is sqrt(1/12) of
> the base cycle time, IIIC (if I integrated correctly). So, if
> the interrupt frequency is 50 kHz, maximum jitter is 10 us,
> and RMS jitter around 6 us.
>
> - This jitter cannot be made any smaller by using a f/f. (Using
> a f/f is the same as halving the output frequency.)

There is a refinement, though, that will reduce jitter: compute the
timer interval, based on the number of timer reference cycles per output
cycle. By carrying over fractions of a cycle, like you do in the fixed
interrupt frequency case, you will, in general, alternate between two
consecutive values for the interrupt duration. The max jitter, then,
would be one timer unit, plus whatever variation there is in interrupt
response (greatly affected by other interrupts of equal or higher
priority interrupts or disabled sections).

> - In order to preserve spectral purity and avoid peaks, it is
> highly advisable to use only odd increments. This makes the
> period longest possible (2^32 cycles).

For a given fixed interrupt frequency and output frequency, though, the
increment is fixed.
>
> A DDS is simple enough to be made with a CPLD or even discrete
> logic. Using a CPLD makes rather high base clock frequencies
> possible (sacrificing the low power consumption and cost, though).

OK. If you aren't otherwise using the CPLD and need the HW solution,
though, an off-the-shelf DDS is probably easier, cheaper, lower power.

Thad

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