Re: Precision PWM in microcontroller

From: Ville Voipio (vvoipio_at_kosh.hut.fi)
Date: 12/30/03 

Date: 30 Dec 2003 10:20:17 +0200

Thad Smith <thadsmith@acm.org> writes:

> Good point. I should have thought of that. The tradeoffs between hw/sw
> are basically low cost vs. low jitter.

Plus low power consumption and small size in the case of a uC.
You can make some rather funny things even with a small uC, if
you do not need a high frequency. I once made a simple synthesizer
with a small AVR ('2313) and a bunch of resistors. Four simultaneous
waveforms were possible.

> There is a refinement, though, that will reduce jitter: compute the
> timer interval, based on the number of timer reference cycles per output
> cycle.

You are right. However, as then the update frequency changes, it becomes
rather difficult to maintain accurate frequency and duty cycle in the
long run. I think it is better either use a pure DDS or a simple
frequency divider (possibly with fractional divisor adjustments).
Mixing the two sounds rather difficult. (But no, I've never calculated
it through...)

> > - In order to preserve spectral purity and avoid peaks, it is
> > highly advisable to use only odd increments. This makes the
> > period longest possible (2^32 cycles).
>
> For a given fixed interrupt frequency and output frequency, though, the
> increment is fixed.

It is. But in case you have enough resolution, this is not a problem.
With 50 kHz update frequency and a 32-bit increment, the smallest frequency
step is around 12 uHz... So, if you sacrifice the last bit, then the
resolution is 24 uHz. Don't look at the crystal, as the heating effect
of your glance will shift the frequency :)

> OK. If you aren't otherwise using the CPLD and need the HW solution,
> though, an off-the-shelf DDS is probably easier, cheaper, lower power.

I don't know. If you need only a digital DDS signal, then the CPLD
solution may be very competitive. Depending on your control system, a
64-cell CPLD should be able to make a 20-bit CPLD. The cost is a
few euros/dollars, and the maximum speed hundreds of MHz with a low-
power chip (such as Xilinx XC2-family or Lattice 4000Z). If you can
store the increment in external shift registers, then a 32-cell CPLD
is enough for a 32-bit DDS. The program is extremely simple.

However, if you need phase control, sinusoidal output, or any other
radioish features, then the integrated solutions are certainly better.
http://www.analog.com/

- Ville 

-- 
Ville Voipio, Dr.Tech., M.Sc. (EE)