Re: PIC + DDS = Frequency Synthesizer?
From: Paul Keinanen (keinanen_at_sci.fi)
Date: 01/02/04
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Date: Fri, 02 Jan 2004 10:18:04 +0200
On 1 Jan 2004 16:15:14 -0800, russ@sotainstruments.com (RussT) wrote:
>What I am trying to do is make a frequency synthesizer that will
>output 1Hz to say 40kHz in 1Hz resolution.
In order to generate a sine signal at the maximum frequency f, you
need to update the DAC at least twice during each cycle, however, in
order to be able to filter out the aliases, the update frequency has
to be at least 2.5f to 3f. Thus, in this case the update rate has to
be at least 100 kHz, thus the software calculation loop cycle time
must be _exactly_ 10 us, thus, if the processor runs at 2 MIPS, there
are 20 instructions available to update the phase accumulator, do the
sine(x), lookup and control the DAC.
However, if the frequency step needs to be exactly 1.0 Hz, then the
phase accumulator has to have at least 17 bits and be clocked at
131.072 kHz and a new value must be outputed every 7.62939453125 us,
thus with a 2 MIPS processor speed 15.258... instructions are
available. In practice you would have to tune the CPU crystal
frequency in order to have an integer number of instructions for each
software loop cycle.
>I need to input via a
>keypad, and have an LCD display show me the inputted frequency.
If no high frequency timer interrupts or a free running hardware
counters are available, then the software calculation loop must
contains exactly the same amount of CPU clock cycles during each
iteration. This means no conditional branching (other than constant
loop counting) or if a conditional loop is used, in cases the branch
is _not_ taken, some dummy instructions must be included that
consumes_exactly_ the same number of clock cycles as the other path
when the conditional branch is taken.
How you are going to handle the keyboard and display during the
available 15 instructions in addition to the DDS is a mystery. You can
not simply handle these every 100th main loop iteration, since this
would upset the timing.
>I know
>virtually zero about assembly language!
Then I suggest that you should learn it before going any further with
this project.
>I do not mind using 2 x
>PICs for the interface and control.
It might be doable if the phase accumulator increment is transferred
through parallel ports from one controller to the other and the
parallel ports can be read with a single instruction (to avoid race
conditions, if the user interface is currently changing the value).
I would really suggest that you should look for a faster processor,
preferably with a high frequency timer interrupt (in which case the
DAC can be written during the interrupt service routine without too
much jitter) or at least contain a free running high resolution
counter (and use a busy wait to wait for a specific value to be
reached). By using these kinds of tricks, the actual calculation time
does not have to be _exactly_ the cycle time, but now it can (and
must) be shorter than the DAC update interval.
Paul
- Previous message: Jim Stewart: "Re: FAT16 help needed!!!"
- In reply to: RussT: "PIC + DDS = Frequency Synthesizer?"
- Next in thread: jim granville: "Re: PIC + DDS = Frequency Synthesizer? [LZ87010]"
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