Re: Schematic Edition Tool : Suggestions

From: Subroto Datta (sdatta_at_altera.com)
Date: 03/16/04 

Date: Tue, 16 Mar 2004 13:55:15 GMT

The Quartus product from Altera will suit your needs, and includes a
schematic editor with netlisting capabilities.. The Quartus design entry
system allows you to mix and match VHDL, Verilog and Schematics. The
product however does not support the MacOS, but will meet all the other
requirements, and is widely used by universities today. The built in text
editor has support for HDL language templates, and the language parser has
good error location capabilities into the Text Editor.

More information about the University program can be found at:
http://www.altera.com/education/univ/unv-index.html

A free version of the Tool can be downloaded at:
http://www.altera.com/education/univ/software/unv-software.html

- Subroto Datta
Altera Corp.

"Francisco Camarero" <nospam@nospam.com> wrote in message
news:4056A867.9351BC4D@nospam.com...
>
>
> Hello !
>
> We are an academic institution teaching our students VLSI design, from
FPGA
> to full custom ASIC. We have put great value on teaching VHDL during the
> past years with very good results from our students.
>
> However, we have the impression that these students have difficulties
> working with schematics as tools to document and express their
> architectural ideas, in part because we did not provide them with such a
> schematic edition tool and thus, we are currently thinking about adding
> such a tool to our design flow.
>
> Among the requirements that we have collected for such a tool would be:
>
> - real schematic edition tool, and not just a drawing tool, i.e:
> - recognizes and keep the connectivity
> - understands connectors and inversion bubbles
> - can select whole nets and name them
> - is able to work with hierarchical schematics
> - makes a graphic difference between scalars and vectors (buses)
>
> - available for different plattforms: Wintel, Linux, Mac OSX
>
> - from the cost viewpoint, affordable by students, i.e: no high-end tool
>
> - a library with block level (adder, multiplier, ALU, registers, datapath
> elements, memory, etc.) symbols is available, or can easily be buit.
>
> - the tool must be able to netlist any schematic hierarchy into a VHDL
> skeleton with entities declaration, instantiation statements and
> architecture templates so that it support the VHDL code writing.
>
> Any suggestions?
>
>
> Fran

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