Re: Problems with JTAG and LH79520

From: db (javaguy11111_at_yahoo.com)
Date: 04/16/04 

Date: 15 Apr 2004 20:57:49 -0700

I was able to get confirmation of a bit off problem. I have another
board that I built with two Xilinx CPLD's and chained together. While
running the IDCODE opcode I was able to get one of the CPLD's to
produce a correct IDCODE response when I offset the command by one
bit.

I tried to see if I could tweak the java code to control when the data
was getting latched in, but that did not work. So I will have to get
back into the the hdl. I have found a TAP core on the opencores.org
website, that I can use to simulate with the hdl code I have written.
I will let you know what I find.

Cheers,
Damon

pablobleyer@hotmail.com (Pablo Bleyer Kocik) wrote in message news:<bb2f07d6.0404150751.222a3155@posting.google.com>...
> javaguy11111@yahoo.com (db) wrote in message news:<903bda3b.0404141815.52cc6641@posting.google.com>...
> > I did realize today that I have been getting the IDCODE if do as in
> > the IEEE1149, by going to test-logic-reset and then shifting out the
> > result from the data register.
> > Still the idcode and other instructions are not working as I would
> > expect them to.
>
> Your signal sequencer is most probably correct then. But if you screw
> things up later you will continue screwing them thereafter (been
> there, done that ;^)
>
> > LH79520. TMS and TDI values are available on the up clock of TCK and
> > TDO is read after the down clock.
>
> But how is your clock between state transitions? It really doesn't
> matter much if you are consistent. Using TCK idle-high is better to
> ease some timings.
>
> > > - Check your TAP state machine sequencing. How are you exiting TAP states?
> > > How are you driving TDI and TCK in the last bit access of the shift states?
> > > Are you exiting to RUN/TEST_IDLE in order to run JTAG commands?
> >
> > Basically the sequence I am using is:
> > run_test_idle().select_dr_scan().select_ir_scan().capture_ir().
> > Then I clock in tdi data on shift_ir(),
> > then I do
> > exit1_ir().update_ir().run_test_idle().select_dr_scan().capture_dr()
> >
> >
> > and shift the data out.
> > I have tried numerous variations on this to try to tease out any
> > errors with being off a bit.
>
> You still don't tell me how you are exiting the shift states. Note
> that the last bit should be shifted in parallel with toggling TMS to
> exit the shift state, otherwise data will roll over and you will shift
> wrong instructions. This is a common misconception about JTAG.
>
> If you post a detailed diagram of the JTAG signals sequencing that
> would be enlightening.
>
> > > - Check your bit ordering. Vendors often publish different bit orders and
> > > swap (MSB->LSB or LSB->MSB) descriptions. Check your JTAG instruction
> > > length.
> >
> > I set up an eight bit counter to cycle through all possible
> > instruction combinations to take into account anything up to 2 bit
> > synchronization error.
> > I still do not see anything being placed between tdi and tdo that
> > would correspond to the opcodes listed in the bsdl.
>
> It won't matter how much you permutate your instructions if you are
> shifting them erroneously ;^)
>
> Cheers!