Re: hobby project - 16 bit digital audio mixer using m68k

From: Paul Keinanen (keinanen_at_sci.fi)
Date: 05/17/04

  • Next message: Stephen Pelc: "Re: 'Real time' Wireless communication (Fencing scoring)" 
    Date: Mon, 17 May 2004 09:45:58 +0300

    On 16 May 2004 22:06:01 -0700, abmiller@vt.edu (Alexander Miller)
    wrote:

    >As a hobbyist project I am planning on constructing a digital audio
    >mixer using a M68000 processor,

    Find out the clock frequency for the original 68K processor. Find out
    how many clock cycles are required by average instructions. Now you
    can calculate the average number of instructions are available each
    second. Divide this figure with 48000 (your sample rate) and you know
    how many instructions are available to process each sample.

    I don't remember, if the original 68K already had a fast multiplier,
    but since you are going to need at least two multiplications for each
    cycle, check out how many clock cycles are required by the
    multiplications.
      
    >along with some 16 bit serial A/D
    >(MAX195) and D/A (MAX542) converters from Maxim.

    Typically serial converters may require multiple machine instructions
    to handle each sample, thus reducing the number of instructions
    available for the actually processing of the audio sample.

    You may be able to build a simple main loop, which reads the ADCs,
    performs some simple operations on the two audio samples and write the
    result to a DAC. If the loop repetition rate is 48 kHz or something
    much less is hard to tell, without doing the actual calculations.

    >I will probably use a M68681 as a UART;

    And when did you intend to find the time to service this ?

    >also, I would like to use an analog fader (pot)
    >fed into an 8 bit parallel ADC as the level control for each input
    >channel.

    This still consumes the available cycles for each audio sample. If you
    are using some kind of SAR ADC, it might be a good idea to read only
    one bit during each 48 kHz cycle, thus, the 8 bit SAR sample rate
    would be 6 kHz or less, but it would not cause too much variation in
    the main loop cycle times.

    I would suggest using some more modern processor requiring less
    external hardware and with more computing power, so that you have a
    decent number of machine instructions available to process each
    sample.

    Paul

  • Next message: Stephen Pelc: "Re: 'Real time' Wireless communication (Fencing scoring)"

    Relevant Pages

    • Re: clock cycle calculations
      ... I am trying to calculate clock cycles per instructions by running the ... Perhaps you want to use these numbers to compute the total execution time of some longer sequence of instructions, by adding up the number of cycles for each instruction in the sequence? ...
      (comp.arch.embedded)
    • Re: Lies, damn lies and benchmarks
      ... When running using just the 16-bit registers, ... extra cycles when run on the 386 over the 286 (these were mostly system ... instructions which didn't get run too often anyways), ... The FPU was another story, the 287 FPU was usually run at an asynchronous ...
      (comp.security.misc)
    • Re: [PATCH RFC/RFB] x86_64, i386: interrupt dispatch changes
      ... cycles to the bus. ... LOCK slowness is not because of the bus. ... maybe 150-200 regular pipelined, superscalar instructions. ...
      (Linux-Kernel)
    • Re: SSE2-Sort within a register
      ... register files. ... cycles. ... 128 bit SSEinstructions are split into Doubles ... Most 128 bit SSE and SSE2 ...
      (comp.lang.asm.x86)
    • Re: Optimization Questions
      ... cycles you'd save would be more than offset by the cycles you'd burn ... instructions go through port 0 and port 1. ... a 16-bit register, writing one afterwards will be fast. ... Pre-read the value in EAX ...
      (comp.lang.asm.x86)