Re: "What time is it?" aksed the microcontroller

From: Paul Keinanen (
Date: 05/23/04

Date: Mon, 24 May 2004 00:01:37 +0300

On Sun, 23 May 2004 10:07:44 -0700, Richard <> wrote:

>Paul Keinanen wrote:
>> If only synchronised time but not absolute time is
>> needed and all devices are connected to the same
>> synchronised national/continental AC power grid,
>> it can be used to generate a common clock signal
>> to all devices.
>Interesting thought, once the initial sync can be achieved.

We once used the serial line break signal at system startup to set all
the clocks in various moving systems in a large hall. The break signal
bypassed the protocol stack and also any UART buffering, so you could
get a quite accurate timing and the system worked for that day after
this single reset.

Some units measured signals that were time stamped at the source.
Based on these measurements the central unit preloaded (on serial
lines) commands to other units which executed the command in the
future, at a time specified in the command frame.

The original system used the same reset principle but relied on
identical processor cards and their CPU clock oscillators to maintain
a common time base. Some units were in boxes, while other in open
frame structures moving around and thus cooled by the air stream and
by the cold winter air coming through the doors when large equipment
were moved in or out from the hall. The CPU clocks could be off by a
second or two only after half an hour requiring a system stop and new

Using the common mains as the clock solved all the problems. No extra
wires were needed, since the mains was needed at each unit anyway.

>The power grid clock is not constant (it varies +/- throughout the day),
>but probably isn't adjusted at a rate that would cause problems for this

Even if the absolute time would be off by a few seconds during the
day, the same error would be at all stations and there would be no
differential error.

>However, I understand that grids are often inter-linked with
>DC, so it may work in some areas but not others.

At least most part of continental Europe is in the same synchronised
area. There are other separate synchronised areas in CIS, Scandinavia
and the British Isles, which are connected to the continental system
by DC links only.

Within the same synchronised area you could use for instance a dial-up
modem in non-error correcting, non-compressed mode at 4800 or 9600
bit/s to reset the clock and then let the systems run independently.
>It all depends on the timing accuracy required. And I wonder how well
>it'd work behind UPS systems - many operate with batteries "on-line"
>(power is rectified, then re-alternated), so the output may not be
>sync'd with the grid.

It will work only if all the equipment are fed by the same UPS.

>> Also the field and line sync pulses from a local
>> TV-transmitter (or TV satellite) has been used in
>> the past to synchronise receivers far apart
>Good point. Even with digital TV, there's bound to be a timing signal
>you could sync from.

With the amount of lip sync and subtitle timing problems in DVB-T, I
very much doubt that you could get any usable timing :-)

>Cellular would be another option.

Depending on the system, something usable might be available.


Relevant Pages

  • Re: Now on 8.2.03i Re: Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic -
    ... "input setup/hold time" is the time required before a clock edge to ... Setup time is the time for the signal to be stable prior to ... live in isolation it is connected to outside devices that may have timing ... the calling module and in the signals used in the submodule. ...
  • Re: Timing violation when initializing "some" FSMs and not others
    ... the clock. ... signals through at least one FF, or if your delays are a significant ... This is not likely to find all or even most timing errors ... Because either there are no timing constraints to check or some ...
  • Re: Post-map simulation: timing violation and delays
    ... up confused in the "things happening in the next clock cycle" thing. ... on different signals in the same process). ... Then I got to the inverter thing, removed some of the timing violations ... I've tried putting in some timing constraints, ...
  • Re: OV7620 image sensor interface with FPGA headache
    ... >pullup resistor and make sure the timing specifications are met and BAM! ... I got the acknowledge signals and the PCLK frequency has doubled ... It is NOT meant as a standard video camera. ... >I'm wondering if this is because the sampling clock my FPGA use is ...
  • Re: same RTL on two same boards giving different behaviour
    ... then that is the source of your timing problem, ... Look at the timing report for the list of clock signals. ... async reset signal that is used to clear flip flops in more than one ...